MICRO

A new hybrid test data compression/ decompression scheme

Sunghoon Chun, Yong Joon Kim, Jung Been Im, Sungho Kang

Research output: Contribution to journalArticle

3 Citations (Scopus)

Abstract

To overcome the limitation of the automatic test equipment (ATE), test data compression/decompression schemes become a more important issue of testing for a system-on-chip (SoC). In order to alleviate the limitation of previous works, a new hybrid test data compression/decompression scheme for an SoC is developed. The new scheme is based on analyzing the factors that influence test parameters: compression ratio and hardware overhead. To improve compression ratio, the proposed scheme, called the Modified Input reduction and CompRessing One block (MICRO), uses the modified input reduction, the one block compression, a novel mapping, and reordering algorithms. Unlike previous approaches using the cyclic scan register architecture, the proposed scheme is to compress original test data and to decompress the compressed test data without the cyclic scan register architecture. Therefore, the proposed scheme leads to high-compression ratio with low-hardware overhead. Experimental results on ISCAS '89 and ITC '99 benchmark circuits prove the efficiency of the new method.

Original languageEnglish
Article number1661607
Pages (from-to)649-654
Number of pages6
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume14
Issue number6
DOIs
Publication statusPublished - 2006 Jun 1

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Data compression
Hardware
Networks (circuits)
Testing
System-on-chip

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

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MICRO : A new hybrid test data compression/ decompression scheme. / Chun, Sunghoon; Kim, Yong Joon; Im, Jung Been; Kang, Sungho.

In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 14, No. 6, 1661607, 01.06.2006, p. 649-654.

Research output: Contribution to journalArticle

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