Minimizing bank selection instructions for partitioned memory architecture

Bernhard Scholz, Bernd Burgstaller, Jingling Xue

Research output: Chapter in Book/Report/Conference proceedingConference contribution

16 Citations (Scopus)

Abstract

Bank switching is a technique that increases the code and data memory in microcontrollers without extending the address buses. Given a program in which variables have been assigned to data banks, we present a novel optimization technique that minimizes the overhead of bank switching through cost-effective placement of bank selection instructions. The optimal placement is controlled by a variety of different objectives, such as runtime, low power, small code size or a combination of these parameters. We have formulated the problem as a form of Partitioned Boolean Quadratic Programming (PBQP).We implemented the optimization as part of a PIC Micro-chip backend and evaluated the approach for several optimization objectives. Our benchmark suite comprises programs from MiBench and DSPStone plus a microcontroller real-time kernel and drivers for microcontroller hardware devices. Our optimization achieved a reduction of program memory space between 2.7% and 18.2%, and an overall improvement with respect to instruction cycles between 5.1% and 28.8%. Our optimization achieved an optimal solution for all benchmark programs.

Original languageEnglish
Title of host publicationCASES 2006
Subtitle of host publicationInternational Conference on Compilers, Architecture and Synthesis for Embedded Systems
Pages201-211
Number of pages11
DOIs
Publication statusPublished - 2006 Dec 1
EventCASES 2006: International Conference on Compilers, Architecture and Synthesis for Embedded Systems - Seoul, Korea, Republic of
Duration: 2006 Oct 222006 Oct 25

Publication series

NameCASES 2006: International Conference on Compilers, Architecture and Synthesis for Embedded Systems

Other

OtherCASES 2006: International Conference on Compilers, Architecture and Synthesis for Embedded Systems
CountryKorea, Republic of
CitySeoul
Period06/10/2206/10/25

Fingerprint

Memory architecture
Microcontrollers
Data storage equipment
Quadratic programming
Hardware
Costs

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Software

Cite this

Scholz, B., Burgstaller, B., & Xue, J. (2006). Minimizing bank selection instructions for partitioned memory architecture. In CASES 2006: International Conference on Compilers, Architecture and Synthesis for Embedded Systems (pp. 201-211). (CASES 2006: International Conference on Compilers, Architecture and Synthesis for Embedded Systems). https://doi.org/10.1145/1176760.1176786
Scholz, Bernhard ; Burgstaller, Bernd ; Xue, Jingling. / Minimizing bank selection instructions for partitioned memory architecture. CASES 2006: International Conference on Compilers, Architecture and Synthesis for Embedded Systems. 2006. pp. 201-211 (CASES 2006: International Conference on Compilers, Architecture and Synthesis for Embedded Systems).
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Scholz, B, Burgstaller, B & Xue, J 2006, Minimizing bank selection instructions for partitioned memory architecture. in CASES 2006: International Conference on Compilers, Architecture and Synthesis for Embedded Systems. CASES 2006: International Conference on Compilers, Architecture and Synthesis for Embedded Systems, pp. 201-211, CASES 2006: International Conference on Compilers, Architecture and Synthesis for Embedded Systems, Seoul, Korea, Republic of, 06/10/22. https://doi.org/10.1145/1176760.1176786

Minimizing bank selection instructions for partitioned memory architecture. / Scholz, Bernhard; Burgstaller, Bernd; Xue, Jingling.

CASES 2006: International Conference on Compilers, Architecture and Synthesis for Embedded Systems. 2006. p. 201-211 (CASES 2006: International Conference on Compilers, Architecture and Synthesis for Embedded Systems).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Scholz B, Burgstaller B, Xue J. Minimizing bank selection instructions for partitioned memory architecture. In CASES 2006: International Conference on Compilers, Architecture and Synthesis for Embedded Systems. 2006. p. 201-211. (CASES 2006: International Conference on Compilers, Architecture and Synthesis for Embedded Systems). https://doi.org/10.1145/1176760.1176786