Minimum delay optimization for domino logic circuits - A coupling-aware approach

Ki Wook Kim, Seongook Jung, Taewhan Kim, Sung Mo Kang

Research output: Contribution to journalArticle

Abstract

Minimum delay associated with the hold time requirement is of concern to circuit designers, since race-through hazards are inherent in any multiple clock organization or clock distribution tree irrespective of clock frequency. The monotonic property of domino logic aggravates the min-delay path failure through coupling-induced speedup. To tackle the min-delay problem for domino logic, we propose a min-delay optimization algorithm considering coupling effects. Experimental results indicate that our algorithm yields a significant increase of min-delay without incurring max-delay violation.

Original languageEnglish
Pages (from-to)203-213
Number of pages11
JournalACM Transactions on Design Automation of Electronic Systems
Volume8
Issue number2
DOIs
Publication statusPublished - 2003 Apr 1

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Logic circuits
Clocks
Hazards
Networks (circuits)

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

Cite this

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Minimum delay optimization for domino logic circuits - A coupling-aware approach. / Kim, Ki Wook; Jung, Seongook; Kim, Taewhan; Kang, Sung Mo.

In: ACM Transactions on Design Automation of Electronic Systems, Vol. 8, No. 2, 01.04.2003, p. 203-213.

Research output: Contribution to journalArticle

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