A design platform for a zero drive load logic inverter consisting of p-channel Si nanowire based transistors, which controlled their operating mode through an implantation into a gate dielectric layer was demonstrated. As a result, a nanowire based class D inverter having a 4.6 gain value at V DD of -20 V was successfully fabricated on a substrate.
All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Ceramics and Composites
- Surfaces, Coatings and Films
- Metals and Alloys
- Materials Chemistry