Modular 128-Channel Δ - ΔΣ Analog Front-End Architecture Using Spectrum Equalization Scheme for 1024-Channel 3-D Neural Recording Microsystems

Sung Yun Park, Jihyun Cho, Kyounghwan Na, Euisik Yoon

Research output: Contribution to journalArticle

11 Citations (Scopus)

Abstract

We report an area- and energy-efficient integrated circuit architecture of a 128-channel Δ-modulated ΔΣ analog front-end (Δ - ΔΣ AFE) for 1024-channel 3-D massive-parallel neural recording microsystems. Our platform has adopted a modularity of 128 channels and consists of eight multi-shank neural probes connected to individual AFEs through interposers in a small form factor. In order to reduce both area and energy consumption in the recording circuits, we implemented a spectrum equalization scheme to take advantage of the inherent spectral characteristics of neural signals, where most of the energy is confined in low frequencies and follows a ∼1/f curve in the spectrum. This allows us to implement the AFE with a relaxed dynamic range by ∼30 dB, thereby contributing to the significant reduction of both energy and area without sacrificing signal integrity. The Δ - ΔΣ AFE was fabricated using 0.18- μm CMOS processes. The single-channel AFE consumes 3.05 μW from 0.5 and 1.0 V supplies in an area of 0.05 mm2 with 63.8-dB signal-to-noise-and-distortion ratio, 3.02 noise efficiency factor (NEF), and 4.56 NEF2VDD. We also have achieved an energy-area product, a figure-of-merit most critical for massive-parallel neural recording systems, of 6.34 fJ/C·s·mm2.

Original languageEnglish
Article number8100720
Pages (from-to)501-514
Number of pages14
JournalIEEE Journal of Solid-State Circuits
Volume53
Issue number2
DOIs
Publication statusPublished - 2018 Feb

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Microsystems
Integrated circuits
Energy utilization
Networks (circuits)

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

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abstract = "We report an area- and energy-efficient integrated circuit architecture of a 128-channel Δ-modulated ΔΣ analog front-end (Δ - ΔΣ AFE) for 1024-channel 3-D massive-parallel neural recording microsystems. Our platform has adopted a modularity of 128 channels and consists of eight multi-shank neural probes connected to individual AFEs through interposers in a small form factor. In order to reduce both area and energy consumption in the recording circuits, we implemented a spectrum equalization scheme to take advantage of the inherent spectral characteristics of neural signals, where most of the energy is confined in low frequencies and follows a ∼1/f curve in the spectrum. This allows us to implement the AFE with a relaxed dynamic range by ∼30 dB, thereby contributing to the significant reduction of both energy and area without sacrificing signal integrity. The Δ - ΔΣ AFE was fabricated using 0.18- μm CMOS processes. The single-channel AFE consumes 3.05 μW from 0.5 and 1.0 V supplies in an area of 0.05 mm2 with 63.8-dB signal-to-noise-and-distortion ratio, 3.02 noise efficiency factor (NEF), and 4.56 NEF2VDD. We also have achieved an energy-area product, a figure-of-merit most critical for massive-parallel neural recording systems, of 6.34 fJ/C·s·mm2.",
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Modular 128-Channel Δ - ΔΣ Analog Front-End Architecture Using Spectrum Equalization Scheme for 1024-Channel 3-D Neural Recording Microsystems. / Park, Sung Yun; Cho, Jihyun; Na, Kyounghwan; Yoon, Euisik.

In: IEEE Journal of Solid-State Circuits, Vol. 53, No. 2, 8100720, 02.2018, p. 501-514.

Research output: Contribution to journalArticle

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