TY - JOUR
T1 - Monolithic fabrication of electroplated solenoid inductors using three-dimensional photolithography of a thick photoresist
AU - Yoon, Jun Bo
AU - Han, Chul Hi
AU - Yoon, Euisik
AU - Kim, Choong Ki
PY - 1998
Y1 - 1998
N2 - A novel and high-yield fabrication process has been devised for monolithic integration of solenoid inductors. In order to simplify the fabrication steps, we decompose the solenoid inductor into two parts, bottom conductor lines and air bridges. The air bridge is formed as a single body during a single electroplating step. This single-step fabrication of the air bridges is possible by forming a three-dimensional (3D) photoresist mold using multiple exposures with varying exposure depths, followed by a single development step, which realizes the 3D latent image of the unexposed volume in the photoresist. We have successfully fabricated solenoid inductors with and without a magnetic core using this process. This process is easy and simple, so that one can significantly improve the fabrication yield over that achieved by conventional methods. Also, this process has good compatibility with the integrated circuit (IC) process owing to a low process temperature (< 120°C) and the monolithic feature.
AB - A novel and high-yield fabrication process has been devised for monolithic integration of solenoid inductors. In order to simplify the fabrication steps, we decompose the solenoid inductor into two parts, bottom conductor lines and air bridges. The air bridge is formed as a single body during a single electroplating step. This single-step fabrication of the air bridges is possible by forming a three-dimensional (3D) photoresist mold using multiple exposures with varying exposure depths, followed by a single development step, which realizes the 3D latent image of the unexposed volume in the photoresist. We have successfully fabricated solenoid inductors with and without a magnetic core using this process. This process is easy and simple, so that one can significantly improve the fabrication yield over that achieved by conventional methods. Also, this process has good compatibility with the integrated circuit (IC) process owing to a low process temperature (< 120°C) and the monolithic feature.
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U2 - 10.1143/jjap.37.7081
DO - 10.1143/jjap.37.7081
M3 - Article
AN - SCOPUS:0001373380
SN - 0021-4922
VL - 37
SP - 7081
EP - 7085
JO - Japanese Journal of Applied Physics
JF - Japanese Journal of Applied Physics
IS - 12 B
ER -