MTJ based non-volatile flip-flop in deep submicron technology

Youngdon Jung, Jisu Kim, Kyungho Ryu, Scong Ook Jung, Jung Pill Kim, Seung H. Kang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Citations (Scopus)

Abstract

The NVFF (Non-Volatile Flip-flop) using a MTJ is one of the powerful solutions for the low power system. However, the previous NVFF cannot provide a sufficient current to write the data into the MTJ in deep submicron technology. This problem occurs due to the lowered supply voltage (1.1V for core device in 45nm technolog) with technology scaling. It can be resolved by increasing the supply voltage. However, the increased supply voltage causes a reliability problem of the core device. In order to overcome this problem, the proposed write circuit adopts an IO device with an IO supply voltage of 1.8V. In addition, the low-skewed NAND (LS-NAND) is used to efficiently interface the two supply voltage levels of 1.1V and 1.8V and to minimize the short circuit current in the write circuit. In this paper, the NVFF with the proposed write circuit is verified by HSPICE simulation using an industry compatible 45nm model parameter. The write current of the proposed write circuit is 60% greater than that of the previous write circuit and is sufficient for the proper write operation.

Original languageEnglish
Title of host publication2011 International SoC Design Conference, ISOCC 2011
Pages424-427
Number of pages4
Publication statusPublished - 2011 Dec 1
Event8th International SoC Design Conference 2011, ISOCC 2011 - Jeju, Korea, Republic of
Duration: 2011 Nov 172011 Nov 18

Other

Other8th International SoC Design Conference 2011, ISOCC 2011
CountryKorea, Republic of
CityJeju
Period11/11/1711/11/18

Fingerprint

Flip flop circuits
Networks (circuits)
Electric potential
Short circuit currents
Industry

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Jung, Y., Kim, J., Ryu, K., Jung, S. O., Kim, J. P., & Kang, S. H. (2011). MTJ based non-volatile flip-flop in deep submicron technology. In 2011 International SoC Design Conference, ISOCC 2011 (pp. 424-427)
Jung, Youngdon ; Kim, Jisu ; Ryu, Kyungho ; Jung, Scong Ook ; Kim, Jung Pill ; Kang, Seung H. / MTJ based non-volatile flip-flop in deep submicron technology. 2011 International SoC Design Conference, ISOCC 2011. 2011. pp. 424-427
@inproceedings{6651ab50809546baad4a00b5d66eb8e8,
title = "MTJ based non-volatile flip-flop in deep submicron technology",
abstract = "The NVFF (Non-Volatile Flip-flop) using a MTJ is one of the powerful solutions for the low power system. However, the previous NVFF cannot provide a sufficient current to write the data into the MTJ in deep submicron technology. This problem occurs due to the lowered supply voltage (1.1V for core device in 45nm technolog) with technology scaling. It can be resolved by increasing the supply voltage. However, the increased supply voltage causes a reliability problem of the core device. In order to overcome this problem, the proposed write circuit adopts an IO device with an IO supply voltage of 1.8V. In addition, the low-skewed NAND (LS-NAND) is used to efficiently interface the two supply voltage levels of 1.1V and 1.8V and to minimize the short circuit current in the write circuit. In this paper, the NVFF with the proposed write circuit is verified by HSPICE simulation using an industry compatible 45nm model parameter. The write current of the proposed write circuit is 60{\%} greater than that of the previous write circuit and is sufficient for the proper write operation.",
author = "Youngdon Jung and Jisu Kim and Kyungho Ryu and Jung, {Scong Ook} and Kim, {Jung Pill} and Kang, {Seung H.}",
year = "2011",
month = "12",
day = "1",
language = "English",
isbn = "9781457707100",
pages = "424--427",
booktitle = "2011 International SoC Design Conference, ISOCC 2011",

}

Jung, Y, Kim, J, Ryu, K, Jung, SO, Kim, JP & Kang, SH 2011, MTJ based non-volatile flip-flop in deep submicron technology. in 2011 International SoC Design Conference, ISOCC 2011. pp. 424-427, 8th International SoC Design Conference 2011, ISOCC 2011, Jeju, Korea, Republic of, 11/11/17.

MTJ based non-volatile flip-flop in deep submicron technology. / Jung, Youngdon; Kim, Jisu; Ryu, Kyungho; Jung, Scong Ook; Kim, Jung Pill; Kang, Seung H.

2011 International SoC Design Conference, ISOCC 2011. 2011. p. 424-427.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - MTJ based non-volatile flip-flop in deep submicron technology

AU - Jung, Youngdon

AU - Kim, Jisu

AU - Ryu, Kyungho

AU - Jung, Scong Ook

AU - Kim, Jung Pill

AU - Kang, Seung H.

PY - 2011/12/1

Y1 - 2011/12/1

N2 - The NVFF (Non-Volatile Flip-flop) using a MTJ is one of the powerful solutions for the low power system. However, the previous NVFF cannot provide a sufficient current to write the data into the MTJ in deep submicron technology. This problem occurs due to the lowered supply voltage (1.1V for core device in 45nm technolog) with technology scaling. It can be resolved by increasing the supply voltage. However, the increased supply voltage causes a reliability problem of the core device. In order to overcome this problem, the proposed write circuit adopts an IO device with an IO supply voltage of 1.8V. In addition, the low-skewed NAND (LS-NAND) is used to efficiently interface the two supply voltage levels of 1.1V and 1.8V and to minimize the short circuit current in the write circuit. In this paper, the NVFF with the proposed write circuit is verified by HSPICE simulation using an industry compatible 45nm model parameter. The write current of the proposed write circuit is 60% greater than that of the previous write circuit and is sufficient for the proper write operation.

AB - The NVFF (Non-Volatile Flip-flop) using a MTJ is one of the powerful solutions for the low power system. However, the previous NVFF cannot provide a sufficient current to write the data into the MTJ in deep submicron technology. This problem occurs due to the lowered supply voltage (1.1V for core device in 45nm technolog) with technology scaling. It can be resolved by increasing the supply voltage. However, the increased supply voltage causes a reliability problem of the core device. In order to overcome this problem, the proposed write circuit adopts an IO device with an IO supply voltage of 1.8V. In addition, the low-skewed NAND (LS-NAND) is used to efficiently interface the two supply voltage levels of 1.1V and 1.8V and to minimize the short circuit current in the write circuit. In this paper, the NVFF with the proposed write circuit is verified by HSPICE simulation using an industry compatible 45nm model parameter. The write current of the proposed write circuit is 60% greater than that of the previous write circuit and is sufficient for the proper write operation.

UR - http://www.scopus.com/inward/record.url?scp=84863127302&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84863127302&partnerID=8YFLogxK

M3 - Conference contribution

SN - 9781457707100

SP - 424

EP - 427

BT - 2011 International SoC Design Conference, ISOCC 2011

ER -

Jung Y, Kim J, Ryu K, Jung SO, Kim JP, Kang SH. MTJ based non-volatile flip-flop in deep submicron technology. In 2011 International SoC Design Conference, ISOCC 2011. 2011. p. 424-427