Multi-bit flip-flop generation considering multi-corner multi-mode timing constraint

Taehee Lee; Jongwon Yi; Joon Sung Yang

doi:10.1109/ISCAS.2016.7527357

Multi-bit flip-flop generation considering multi-corner multi-mode timing constraint

Taehee Lee, Jongwon Yi, Joon Sung Yang

College of Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

Clock power is a significant portion of chip power in System-on-chip (SoC). Applying Multi-bit flip-flop (MBFF) is capable of providing attractive solution to reduce clock power. To our best knowledge, this is the first work in the literature that considers multi-corner and multi-mode (MCMM) timing constraint for the MBFF generation. This proposed method is applied to five industrial digital intellectual property (IP) blocks of state-of-the-art System-on-chip (SoC). Experimental results show that our proposed MBFF generation algorithm achieves 22% clock power reduction.

Original language	English
Title of host publication	ISCAS 2016 - IEEE International Symposium on Circuits and Systems
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	782-785
Number of pages	4
ISBN (Electronic)	9781479953400
DOIs	https://doi.org/10.1109/ISCAS.2016.7527357
Publication status	Published - 2016 Jul 29
Event	2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016 - Montreal, Canada Duration: 2016 May 22 → 2016 May 25

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	2016-July
ISSN (Print)	0271-4310

Other

Other	2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016
Country	Canada
City	Montreal
Period	16/5/22 → 16/5/25

Bibliographical note

Publisher Copyright:
© 2016 IEEE.

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Access to Document

10.1109/ISCAS.2016.7527357

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Lee, T., Yi, J., & Yang, J. S. (2016). Multi-bit flip-flop generation considering multi-corner multi-mode timing constraint. In ISCAS 2016 - IEEE International Symposium on Circuits and Systems (pp. 782-785). [7527357] (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2016-July). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2016.7527357

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abstract = "Clock power is a significant portion of chip power in System-on-chip (SoC). Applying Multi-bit flip-flop (MBFF) is capable of providing attractive solution to reduce clock power. To our best knowledge, this is the first work in the literature that considers multi-corner and multi-mode (MCMM) timing constraint for the MBFF generation. This proposed method is applied to five industrial digital intellectual property (IP) blocks of state-of-the-art System-on-chip (SoC). Experimental results show that our proposed MBFF generation algorithm achieves 22% clock power reduction.",

author = "Taehee Lee and Jongwon Yi and Yang, {Joon Sung}",

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Lee, T, Yi, J & Yang, JS 2016, Multi-bit flip-flop generation considering multi-corner multi-mode timing constraint. in ISCAS 2016 - IEEE International Symposium on Circuits and Systems., 7527357, Proceedings - IEEE International Symposium on Circuits and Systems, vol. 2016-July, Institute of Electrical and Electronics Engineers Inc., pp. 782-785, 2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016, Montreal, Canada, 16/5/22. https://doi.org/10.1109/ISCAS.2016.7527357

Multi-bit flip-flop generation considering multi-corner multi-mode timing constraint. / Lee, Taehee; Yi, Jongwon; Yang, Joon Sung.

ISCAS 2016 - IEEE International Symposium on Circuits and Systems. Institute of Electrical and Electronics Engineers Inc., 2016. p. 782-785 7527357 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2016-July).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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PY - 2016/7/29

Y1 - 2016/7/29

N2 - Clock power is a significant portion of chip power in System-on-chip (SoC). Applying Multi-bit flip-flop (MBFF) is capable of providing attractive solution to reduce clock power. To our best knowledge, this is the first work in the literature that considers multi-corner and multi-mode (MCMM) timing constraint for the MBFF generation. This proposed method is applied to five industrial digital intellectual property (IP) blocks of state-of-the-art System-on-chip (SoC). Experimental results show that our proposed MBFF generation algorithm achieves 22% clock power reduction.

AB - Clock power is a significant portion of chip power in System-on-chip (SoC). Applying Multi-bit flip-flop (MBFF) is capable of providing attractive solution to reduce clock power. To our best knowledge, this is the first work in the literature that considers multi-corner and multi-mode (MCMM) timing constraint for the MBFF generation. This proposed method is applied to five industrial digital intellectual property (IP) blocks of state-of-the-art System-on-chip (SoC). Experimental results show that our proposed MBFF generation algorithm achieves 22% clock power reduction.

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M3 - Conference contribution

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Lee T, Yi J, Yang JS. Multi-bit flip-flop generation considering multi-corner multi-mode timing constraint. In ISCAS 2016 - IEEE International Symposium on Circuits and Systems. Institute of Electrical and Electronics Engineers Inc. 2016. p. 782-785. 7527357. (Proceedings - IEEE International Symposium on Circuits and Systems). https://doi.org/10.1109/ISCAS.2016.7527357

Multi-bit flip-flop generation considering multi-corner multi-mode timing constraint

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