Abstract
Clock power is a significant portion of chip power in System-on-chip (SoC). Applying Multi-bit flip-flop (MBFF) is capable of providing attractive solution to reduce clock power. To our best knowledge, this is the first work in the literature that considers multi-corner and multi-mode (MCMM) timing constraint for the MBFF generation. This proposed method is applied to five industrial digital intellectual property (IP) blocks of state-of-the-art System-on-chip (SoC). Experimental results show that our proposed MBFF generation algorithm achieves 22% clock power reduction.
Original language | English |
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Title of host publication | ISCAS 2016 - IEEE International Symposium on Circuits and Systems |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 782-785 |
Number of pages | 4 |
ISBN (Electronic) | 9781479953400 |
DOIs | |
Publication status | Published - 2016 Jul 29 |
Event | 2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016 - Montreal, Canada Duration: 2016 May 22 → 2016 May 25 |
Publication series
Name | Proceedings - IEEE International Symposium on Circuits and Systems |
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Volume | 2016-July |
ISSN (Print) | 0271-4310 |
Other
Other | 2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016 |
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Country/Territory | Canada |
City | Montreal |
Period | 16/5/22 → 16/5/25 |
Bibliographical note
Publisher Copyright:© 2016 IEEE.
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering