Abstract
Two-dimensionalmaterials like graphene have great potential to excess the mobility limit of conventional silicon devices. Particularly, MoS2 FETs have high mobility and low off-current simultaneously due to their sizable band-gap. However, large hysteresis in its transfer curve is an obstacle for implementation to logic circuits and switching devices. Here, we report on a multi-layer MoS2 FET using atomic layer deposition Al 2O3 as a gate insulator, showing small hysteresis of 0.86 V. It is thought that, such improvement in the hysteresis attributes to the small trap at the MoS2/Al2O3 interface, and it is confirmed through a constant current stress test.
Original language | English |
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Pages (from-to) | Q67-Q69 |
Journal | ECS Solid State Letters |
Volume | 3 |
Issue number | 10 |
DOIs | |
Publication status | Published - 2014 |
Bibliographical note
Funding Information:This research was supported by the MSIP (Ministry of Science, ICT and Future Planning), Korea under the “IT Consilience Creative Program” (NIPA-2014-H0201-14-1002) supervised by the NIPA (National IT Industry Promotion Agency).
Funding Information:
This research was supported by the MSIP (Ministry of Science, ICT and Future Planning), Korea under the "IT Consilience Creative Program" (NIPA-2014-H0201-14-1002) supervised by the NIPA (National IT Industry Promotion Agency).
All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering