Multi-level cache vulnerability estimation: The first step to protect memory

Yohan Ko, Kyoungwoo Lee

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Cache is one of the most susceptible microarchitectural components against soft errors since cache memory not only takes up the majority of chip area but also is frequently accessed by other microarchitectural components. Several protection techniques have been proposed in order to improve the cache reliability. These cache protections can significantly affect the overall performance of the entire processor. Thus, it is extremely important to quantify the reliability of cache memory with and without protections in order to choose appropriate protection techniques. In this paper, we model the vulnerability estimation with considering generally used protection techniques, such as parity and error correction code, on multi-level cache memory. In common processors, level 1 and 2 caches are protected by parity and error correction code, respectively, but our experimental results reveal several interesting results. First off, parity protection for level 1 instruction cache can be good way to decrease the vulnerability, but it is inefficient for level 1 data cache. In special cases, parity protection for level 1 data cache can worsen the reliability as compared to unprotected cache. Secondly, parity protection for level 2 cache can decrease the vulnerability almost by half with the comparable overheads. For some benchmarks, parity protection for level 2 cache can be as reliable as error correcting code with much less overheads.

Original languageEnglish
Title of host publication2016 IEEE International Conference on Systems, Man, and Cybernetics, SMC 2016 - Conference Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1165-1170
Number of pages6
ISBN (Electronic)9781509018970
DOIs
Publication statusPublished - 2017 Feb 6
Event2016 IEEE International Conference on Systems, Man, and Cybernetics, SMC 2016 - Budapest, Hungary
Duration: 2016 Oct 92016 Oct 12

Publication series

Name2016 IEEE International Conference on Systems, Man, and Cybernetics, SMC 2016 - Conference Proceedings

Other

Other2016 IEEE International Conference on Systems, Man, and Cybernetics, SMC 2016
CountryHungary
CityBudapest
Period16/10/916/10/12

All Science Journal Classification (ASJC) codes

  • Computer Vision and Pattern Recognition
  • Artificial Intelligence
  • Control and Optimization
  • Human-Computer Interaction

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    Ko, Y., & Lee, K. (2017). Multi-level cache vulnerability estimation: The first step to protect memory. In 2016 IEEE International Conference on Systems, Man, and Cybernetics, SMC 2016 - Conference Proceedings (pp. 1165-1170). [7844399] (2016 IEEE International Conference on Systems, Man, and Cybernetics, SMC 2016 - Conference Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SMC.2016.7844399