Cache is one of the most susceptible microarchitectural components against soft errors since cache memory not only takes up the majority of chip area but also is frequently accessed by other microarchitectural components. Several protection techniques have been proposed in order to improve the cache reliability. These cache protections can significantly affect the overall performance of the entire processor. Thus, it is extremely important to quantify the reliability of cache memory with and without protections in order to choose appropriate protection techniques. In this paper, we model the vulnerability estimation with considering generally used protection techniques, such as parity and error correction code, on multi-level cache memory. In common processors, level 1 and 2 caches are protected by parity and error correction code, respectively, but our experimental results reveal several interesting results. First off, parity protection for level 1 instruction cache can be good way to decrease the vulnerability, but it is inefficient for level 1 data cache. In special cases, parity protection for level 1 data cache can worsen the reliability as compared to unprotected cache. Secondly, parity protection for level 2 cache can decrease the vulnerability almost by half with the comparable overheads. For some benchmarks, parity protection for level 2 cache can be as reliable as error correcting code with much less overheads.
|Title of host publication||2016 IEEE International Conference on Systems, Man, and Cybernetics, SMC 2016 - Conference Proceedings|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||6|
|Publication status||Published - 2017 Feb 6|
|Event||2016 IEEE International Conference on Systems, Man, and Cybernetics, SMC 2016 - Budapest, Hungary|
Duration: 2016 Oct 9 → 2016 Oct 12
|Name||2016 IEEE International Conference on Systems, Man, and Cybernetics, SMC 2016 - Conference Proceedings|
|Other||2016 IEEE International Conference on Systems, Man, and Cybernetics, SMC 2016|
|Period||16/10/9 → 16/10/12|
Bibliographical noteFunding Information:
This research was supported in part by Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Science, ICT and future Planning (NRF-2015R1A2A1A15053435), by Next-Generation Information Computing Development Program through the NRF funded by the Ministry of Science, ICT Future Planning (NRF-2015M3C4A7065522), and by MSIP under the Research Project on High Performance and Scalable Manycore Operating System (#14-824-09-011).
© 2016 IEEE.
All Science Journal Classification (ASJC) codes
- Computer Vision and Pattern Recognition
- Artificial Intelligence
- Control and Optimization
- Human-Computer Interaction