Multi-operation-based constrained random verification for on-chip memory

Hyeonuk Son, Jaewon Jang, Heetae Kim, Sungho Kang

Research output: Contribution to journalArticle

Abstract

Current verification methods for on-chip memory have been implemented using coverpoints that are generated based on a single operation. These coverpoints cannot consider the influence of other memory banks in a busy state. In this paper, we propose a method in which the coverpoints account for all operations executed on different memory banks. In addition, a new constrained random vector generation method is proposed to reduce the required random vectors for the multi-operation-based coverpoints. The simulation results on NAND flash memory show 100% coverage with 496,541 constrained random vectors indicating a reduction of 96.4% compared with conventional random vectors. Index Terms—Constrained random verification (CRV), functional verification, coverpoint, NAND flash, constrained random vectors.

Original languageEnglish
Pages (from-to)423-426
Number of pages4
JournalJournal of Semiconductor Technology and Science
Volume15
Issue number3
DOIs
Publication statusPublished - 2015 Jan 1

Fingerprint

Data storage equipment
Flash memory

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

@article{f5d1975b03584eacbc214592d3394a95,
title = "Multi-operation-based constrained random verification for on-chip memory",
abstract = "Current verification methods for on-chip memory have been implemented using coverpoints that are generated based on a single operation. These coverpoints cannot consider the influence of other memory banks in a busy state. In this paper, we propose a method in which the coverpoints account for all operations executed on different memory banks. In addition, a new constrained random vector generation method is proposed to reduce the required random vectors for the multi-operation-based coverpoints. The simulation results on NAND flash memory show 100{\%} coverage with 496,541 constrained random vectors indicating a reduction of 96.4{\%} compared with conventional random vectors. Index Terms—Constrained random verification (CRV), functional verification, coverpoint, NAND flash, constrained random vectors.",
author = "Hyeonuk Son and Jaewon Jang and Heetae Kim and Sungho Kang",
year = "2015",
month = "1",
day = "1",
doi = "10.5573/JSTS.2015.15.3.423",
language = "English",
volume = "15",
pages = "423--426",
journal = "Journal of Semiconductor Technology and Science",
issn = "1598-1657",
publisher = "Institute of Electronics Engineers of Korea",
number = "3",

}

Multi-operation-based constrained random verification for on-chip memory. / Son, Hyeonuk; Jang, Jaewon; Kim, Heetae; Kang, Sungho.

In: Journal of Semiconductor Technology and Science, Vol. 15, No. 3, 01.01.2015, p. 423-426.

Research output: Contribution to journalArticle

TY - JOUR

T1 - Multi-operation-based constrained random verification for on-chip memory

AU - Son, Hyeonuk

AU - Jang, Jaewon

AU - Kim, Heetae

AU - Kang, Sungho

PY - 2015/1/1

Y1 - 2015/1/1

N2 - Current verification methods for on-chip memory have been implemented using coverpoints that are generated based on a single operation. These coverpoints cannot consider the influence of other memory banks in a busy state. In this paper, we propose a method in which the coverpoints account for all operations executed on different memory banks. In addition, a new constrained random vector generation method is proposed to reduce the required random vectors for the multi-operation-based coverpoints. The simulation results on NAND flash memory show 100% coverage with 496,541 constrained random vectors indicating a reduction of 96.4% compared with conventional random vectors. Index Terms—Constrained random verification (CRV), functional verification, coverpoint, NAND flash, constrained random vectors.

AB - Current verification methods for on-chip memory have been implemented using coverpoints that are generated based on a single operation. These coverpoints cannot consider the influence of other memory banks in a busy state. In this paper, we propose a method in which the coverpoints account for all operations executed on different memory banks. In addition, a new constrained random vector generation method is proposed to reduce the required random vectors for the multi-operation-based coverpoints. The simulation results on NAND flash memory show 100% coverage with 496,541 constrained random vectors indicating a reduction of 96.4% compared with conventional random vectors. Index Terms—Constrained random verification (CRV), functional verification, coverpoint, NAND flash, constrained random vectors.

UR - http://www.scopus.com/inward/record.url?scp=84936747069&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84936747069&partnerID=8YFLogxK

U2 - 10.5573/JSTS.2015.15.3.423

DO - 10.5573/JSTS.2015.15.3.423

M3 - Article

VL - 15

SP - 423

EP - 426

JO - Journal of Semiconductor Technology and Science

JF - Journal of Semiconductor Technology and Science

SN - 1598-1657

IS - 3

ER -