Multicore speedup models using frequency scaling with fixed power budget

Seungwon Lee, Seung Hun Kim, Won Woo Ro

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Utilization of a core with delay faults by frequency scaling reduces performance degradation in a multicore processor. When the frequency of a delay fault core is decreased, frequencies of the rest cores can be increased within a fixed power budget since the amount of dynamic power is proportional to the clock frequency. We propose two speedup models based on modified Amdahl's law for the frequency scaling of a multicore architecture. From the models, we derive an attainable maximum speedup of a multicore processor with a delay fault core.

Original languageEnglish
Title of host publication13th International Conference on Electronics, Information, and Communication, ICEIC 2014 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781479939428
DOIs
Publication statusPublished - 2014 Sep 30
Event13th International Conference on Electronics, Information, and Communication, ICEIC 2014 - Kota Kinabalu, Malaysia
Duration: 2014 Jan 152014 Jan 18

Publication series

Name13th International Conference on Electronics, Information, and Communication, ICEIC 2014 - Proceedings

Other

Other13th International Conference on Electronics, Information, and Communication, ICEIC 2014
CountryMalaysia
CityKota Kinabalu
Period14/1/1514/1/18

Bibliographical note

Publisher Copyright:
© 2014 IEEE.

All Science Journal Classification (ASJC) codes

  • Control and Systems Engineering
  • Electrical and Electronic Engineering

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