Multilayer power delivery network design for high-speed microprocessor system

Seong Geun Park; Ji Seong Kim; Jong Gwan Yook; Han Kyu Park

Multilayer power delivery network design for high-speed microprocessor system

Seong Geun Park, Ji Seong Kim, Jong Gwan Yook, Han Kyu Park

Department of Electrical and Electronic Engineering

Research output: Contribution to journal › Conference article › peer-review

5 Citations (Scopus)

Abstract

In this paper, an efficient modeling method for arbitrary shaped multi-layer power distribution network is proposed based on the method of transmission line grid model. In addition, a pre-layout design approach for the high-speed microprocessor is proposed. For arbitrary-shaped multi-layer PCB stack up configuration as well as selection and placement of decoupling capacitors, an effective solution for reducing SSN and EMI is obtained by modeling and simulation of complete power distribution system.

Original language	English
Pages (from-to)	1613-1618
Number of pages	6
Journal	Proceedings - Electronic Components and Technology Conference
Publication status	Published - 2003
Event	53rd Electronic Components and Technology Conference 2003 - New Orleans LA, United States Duration: 2003 May 27 → 2003 May 30

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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@article{b1709a0c98da4f348b87ab680fac63d6,

title = "Multilayer power delivery network design for high-speed microprocessor system",

abstract = "In this paper, an efficient modeling method for arbitrary shaped multi-layer power distribution network is proposed based on the method of transmission line grid model. In addition, a pre-layout design approach for the high-speed microprocessor is proposed. For arbitrary-shaped multi-layer PCB stack up configuration as well as selection and placement of decoupling capacitors, an effective solution for reducing SSN and EMI is obtained by modeling and simulation of complete power distribution system.",

author = "Park, {Seong Geun} and Kim, {Ji Seong} and Yook, {Jong Gwan} and Park, {Han Kyu}",

year = "2003",

language = "English",

pages = "1613--1618",

journal = "Proceedings - Electronic Components and Technology Conference",

issn = "0569-5503",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "53rd Electronic Components and Technology Conference 2003 ; Conference date: 27-05-2003 Through 30-05-2003",

}

TY - JOUR

T1 - Multilayer power delivery network design for high-speed microprocessor system

AU - Park, Seong Geun

AU - Kim, Ji Seong

AU - Yook, Jong Gwan

AU - Park, Han Kyu

PY - 2003

Y1 - 2003

N2 - In this paper, an efficient modeling method for arbitrary shaped multi-layer power distribution network is proposed based on the method of transmission line grid model. In addition, a pre-layout design approach for the high-speed microprocessor is proposed. For arbitrary-shaped multi-layer PCB stack up configuration as well as selection and placement of decoupling capacitors, an effective solution for reducing SSN and EMI is obtained by modeling and simulation of complete power distribution system.

AB - In this paper, an efficient modeling method for arbitrary shaped multi-layer power distribution network is proposed based on the method of transmission line grid model. In addition, a pre-layout design approach for the high-speed microprocessor is proposed. For arbitrary-shaped multi-layer PCB stack up configuration as well as selection and placement of decoupling capacitors, an effective solution for reducing SSN and EMI is obtained by modeling and simulation of complete power distribution system.

UR - http://www.scopus.com/inward/record.url?scp=0038350319&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0038350319&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:0038350319

SP - 1613

EP - 1618

JO - Proceedings - Electronic Components and Technology Conference

JF - Proceedings - Electronic Components and Technology Conference

SN - 0569-5503

T2 - 53rd Electronic Components and Technology Conference 2003

Y2 - 27 May 2003 through 30 May 2003

ER -

Multilayer power delivery network design for high-speed microprocessor system

Abstract

All Science Journal Classification (ASJC) codes

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