Abstract
In this paper, an efficient modeling method for arbitrary shaped multi-layer power distribution network is proposed based on the method of transmission line grid model. In addition, a pre-layout design approach for the high-speed microprocessor is proposed. For arbitrary-shaped multi-layer PCB stack up configuration as well as selection and placement of decoupling capacitors, an effective solution for reducing SSN and EMI is obtained by modeling and simulation of complete power distribution system.
| Original language | English |
|---|---|
| Pages (from-to) | 1613-1618 |
| Number of pages | 6 |
| Journal | Proceedings - Electronic Components and Technology Conference |
| Publication status | Published - 2003 Jul 17 |
| Event | 53rd Electronic Components and Technology Conference 2003 - New Orleans LA, United States Duration: 2003 May 27 → 2003 May 30 |
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All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering
Cite this
Park, S. G., Kim, J. S., Yook, J. G., & Park, H. K. (2003). Multilayer power delivery network design for high-speed microprocessor system. Proceedings - Electronic Components and Technology Conference, 1613-1618.