Spin-transfer-torque random access memory (STT-RAM) has attracted much research interest because of its characteristics of nonvolatility (i.e., zero standby power) and small cell size (i.e., high density and high performance). As the technology node is scaled down, however, the sensing margin of the STT-RAM is degraded because of the increased process variation and reduced supply voltage. To improve the sensing margin, this brief focuses on a reference scheme design capable of reducing the reference resistance distribution. A multiple-cell reference (MCR) scheme is proposed that achieves the narrow reference resistance distribution. Moreover, the MCR scheme does not exhibit parasitic mismatch, regularity problem, read disturbance, and write current degradation, and it also has small area overhead.
|Number of pages||5|
|Journal||IEEE Transactions on Very Large Scale Integration (VLSI) Systems|
|Publication status||Published - 2016 Sep|
Bibliographical notePublisher Copyright:
© 2016 IEEE.
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering