With a development of process technology, a memory density has been increased. However, a smaller feature size makes the memory susceptible to soft errors. For reliability enhancement, ECC with single bit error correction and double bit error detection is widely used. As multiple bit cell upset become dominant, there is a need for stronger ECC. ECC such as RS or BCH code requires significantly large overhead and longer latency. To overcome the problem, this paper introduces an unequal protection ECC assigning stronger level of protection to weak memory cells and normal level to normal cells. Information from manufacturing characterization test is utilized to identify weak memory cells with low design margins. Instead of equally treating all memory cells, the proposed ECC focuses more on the weak cells since they are more susceptible to soft errors. Compared to conventional ECCs, experimental results show that the proposed ECC considerably enhances memory reliability with the same code length.
|Title of host publication||Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||6|
|Publication status||Published - 2017 May 11|
|Event||20th Design, Automation and Test in Europe, DATE 2017 - Swisstech, Lausanne, Switzerland|
Duration: 2017 Mar 27 → 2017 Mar 31
|Name||Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017|
|Other||20th Design, Automation and Test in Europe, DATE 2017|
|Period||17/3/27 → 17/3/31|
Bibliographical notePublisher Copyright:
© 2017 IEEE.
All Science Journal Classification (ASJC) codes
- Computer Networks and Communications
- Hardware and Architecture
- Safety, Risk, Reliability and Quality