Abstract
In recent years, the demand for NAND flash-based storage devices has rapidly increased because of the popularization of various portable devices. NAND flash memory (NFM) offers many advantages, such as nonvolatility, high performance, the small form factor, and low-power consumption, while achieving high chip integration with a specialized architecture for bulk data access. A unit of NFM's read and program operations, the page, has continuously grown. Although increasing page size reduces costs, it adversely affects performance because of the resultant side effects, such as fragmentation and wasted space, caused by the incongruity of data and page sizes. To address this issue, we propose a multiple-page-size NFM architecture and its management. Our method dramatically improves write performance through adopting multiple page sizes without requiring additional area overhead or manufacturing processes. Based on the experimental results, the proposed NFM improves write latency and NFM lifetime by up to 65% and 62%, respectively, compared with the single-page-size NFM.
| Original language | English |
|---|---|
| Article number | 7066966 |
| Pages (from-to) | 764-768 |
| Number of pages | 5 |
| Journal | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
| Volume | 24 |
| Issue number | 2 |
| DOIs | |
| Publication status | Published - 2016 Feb |
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All Science Journal Classification (ASJC) codes
- Software
- Hardware and Architecture
- Electrical and Electronic Engineering
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NAND Flash Memory with Multiple Page Sizes for High-Performance Storage Devices. / Kim, Jin Young; Park, Sang Hoon; Seo, Hyeokjun; Song, Ki Whan; Yoon, Sungroh; Chung, Eui Young.
In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 24, No. 2, 7066966, 02.2016, p. 764-768.Research output: Contribution to journal › Article
TY - JOUR
T1 - NAND Flash Memory with Multiple Page Sizes for High-Performance Storage Devices
AU - Kim, Jin Young
AU - Park, Sang Hoon
AU - Seo, Hyeokjun
AU - Song, Ki Whan
AU - Yoon, Sungroh
AU - Chung, Eui Young
PY - 2016/2
Y1 - 2016/2
N2 - In recent years, the demand for NAND flash-based storage devices has rapidly increased because of the popularization of various portable devices. NAND flash memory (NFM) offers many advantages, such as nonvolatility, high performance, the small form factor, and low-power consumption, while achieving high chip integration with a specialized architecture for bulk data access. A unit of NFM's read and program operations, the page, has continuously grown. Although increasing page size reduces costs, it adversely affects performance because of the resultant side effects, such as fragmentation and wasted space, caused by the incongruity of data and page sizes. To address this issue, we propose a multiple-page-size NFM architecture and its management. Our method dramatically improves write performance through adopting multiple page sizes without requiring additional area overhead or manufacturing processes. Based on the experimental results, the proposed NFM improves write latency and NFM lifetime by up to 65% and 62%, respectively, compared with the single-page-size NFM.
AB - In recent years, the demand for NAND flash-based storage devices has rapidly increased because of the popularization of various portable devices. NAND flash memory (NFM) offers many advantages, such as nonvolatility, high performance, the small form factor, and low-power consumption, while achieving high chip integration with a specialized architecture for bulk data access. A unit of NFM's read and program operations, the page, has continuously grown. Although increasing page size reduces costs, it adversely affects performance because of the resultant side effects, such as fragmentation and wasted space, caused by the incongruity of data and page sizes. To address this issue, we propose a multiple-page-size NFM architecture and its management. Our method dramatically improves write performance through adopting multiple page sizes without requiring additional area overhead or manufacturing processes. Based on the experimental results, the proposed NFM improves write latency and NFM lifetime by up to 65% and 62%, respectively, compared with the single-page-size NFM.
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UR - http://www.scopus.com/inward/citedby.url?scp=84925853802&partnerID=8YFLogxK
U2 - 10.1109/TVLSI.2015.2409055
DO - 10.1109/TVLSI.2015.2409055
M3 - Article
AN - SCOPUS:84925853802
VL - 24
SP - 764
EP - 768
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SN - 1063-8210
IS - 2
M1 - 7066966
ER -