NANDFlashSim

High-fidelity, microarchitecture-aware NAND flash memory simulation

Myoungsoo Jung, Wonil Choi, Shuwen Gao, Ellis Herbert Wilson, David Donofrio, John Shalf, Mahmut Taylan Kandemir

Research output: Contribution to journalArticle

5 Citations (Scopus)

Abstract

As the popularity of NAND flash expands in arenas from embedded systems to high-performance computing, a high-fidelity understanding of its specific properties becomes increasingly important. Further, with the increasing trend toward multiple-die, multiple-plane architectures and high-speed interfaces, flash memory systems are expected to continue to scale and cheapen, resulting in their broader proliferation. However, when designing NAND-based devices, making decisions about the optimal system configuration is nontrivial, because flash is sensitive to a number of parameters and suffers from inherent latency variations, and no available tools suffice for studying these nuances. The parameters include the architectures, such as multidie and multiplane, diverse node technologies, bit densities, and cell reliabilities. Therefore, we introduce NANDFlashSim, a high-fidelity, latency-variation-aware, and highly configurable NAND-flash simulator, which implements a detailed timing model for 16 state-of-the-art NAND operations. Using NANDFlashSim, we notably discover the following. First, regardless of the operation, reads fail to leverage internal parallelism. Second, MLC provides lower I/O bus contention than SLC, but contention becomes a serious problem as the number of dies increases. Third, many-die architectures outperform many-plane architectures for disk-friendly workloads. Finally, employing a high-performance I/O bus or an increased page size does not enhance energy savings. Our simulator is available at http://nfs.camelab.org.

Original languageEnglish
Article number6
JournalACM Transactions on Storage
Volume12
Issue number2
DOIs
Publication statusPublished - 2016 Feb 1

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Flash memory
Simulators
Optimal systems
Embedded systems
Energy conservation
Decision making

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

Cite this

Jung, M., Choi, W., Gao, S., Wilson, E. H., Donofrio, D., Shalf, J., & Kandemir, M. T. (2016). NANDFlashSim: High-fidelity, microarchitecture-aware NAND flash memory simulation. ACM Transactions on Storage, 12(2), [6]. https://doi.org/10.1145/2700310
Jung, Myoungsoo ; Choi, Wonil ; Gao, Shuwen ; Wilson, Ellis Herbert ; Donofrio, David ; Shalf, John ; Kandemir, Mahmut Taylan. / NANDFlashSim : High-fidelity, microarchitecture-aware NAND flash memory simulation. In: ACM Transactions on Storage. 2016 ; Vol. 12, No. 2.
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Jung, M, Choi, W, Gao, S, Wilson, EH, Donofrio, D, Shalf, J & Kandemir, MT 2016, 'NANDFlashSim: High-fidelity, microarchitecture-aware NAND flash memory simulation', ACM Transactions on Storage, vol. 12, no. 2, 6. https://doi.org/10.1145/2700310

NANDFlashSim : High-fidelity, microarchitecture-aware NAND flash memory simulation. / Jung, Myoungsoo; Choi, Wonil; Gao, Shuwen; Wilson, Ellis Herbert; Donofrio, David; Shalf, John; Kandemir, Mahmut Taylan.

In: ACM Transactions on Storage, Vol. 12, No. 2, 6, 01.02.2016.

Research output: Contribution to journalArticle

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