NANDFlashSim

Intrinsic latency variation aware NAND flash memory system modeling and simulation at microarchitecture level

Myoungsoo Jung, Ellis Herbert Wilson, David Donofrio, John Shalf, Mahmut Taylan Kandemir

Research output: Chapter in Book/Report/Conference proceedingConference contribution

33 Citations (Scopus)

Abstract

As NAND flash memory becomes popular in diverse areas ranging from embedded systems to high performance computing, exposing and understanding flash memory's performance, energy consumption, and reliability becomes increasingly important. Moreover, with an increasing trend towards multiple-die, multiple-plane architectures and high speed interfaces, high performance NAND flash memory systems are expected to continue to scale. This scaling should further reduce costs and thereby widen proliferation of devices based on the technology. However, when designing NAND flash-based devices, making decisions about the optimal system configuration is non-trivial because NAND flash is sensitive to a large number of parameters, and some parameters exhibit significant latency variations. Such parameters include varying architectures such as multi-die and multi-plane, and a host of factors that affect performance, energy consumption, diverse node technology, and reliability. Unfortunately, there are no public domain tools for high-fidelity, microarchitecture level NAND flash memory simulation in existence to assist with making such decisions. Therefore, we introduce NANDFlashSim; a latency variation-aware, detailed, and highly configurable NAND flash simulation model. NANDFlashSim implements a detailed timing model for operations in sixteen state-of-the-art NAND flash operation mode combinations. In addition, NANDFlashSim models energies and reliability of NAND flash memory based on statistics. From our comprehensive experiments using NANDFlashSim, we found that 1) most read cases were unable to leverage the highly-parallel internal architecture of NAND flash regardless of the NAND flash operation mode, 2) the main source of this performance bottleneck is I/O bus activity, not NAND flash activity itself, 3) multi-level-cell NAND flash provides lower I/O bus resource contention than single-level-cell NAND flash, but the resource contention becomes a serious problem as the number of die increases, and 4) preference to employ many dies rather than to employ many planes promises better performance in disk-friendly real workloads. The simulator can be downloaded from http://www.cse.psu.edu/~mqj5086/nfs.

Original languageEnglish
Title of host publication2012 IEEE 28th Symposium on Mass Storage Systems and Technologies, MSST 2012
DOIs
Publication statusPublished - 2012 Sep 18
Event2012 IEEE 28th Symposium on Mass Storage Systems and Technologies, MSST 2012 - Pacific Grove, CA, United States
Duration: 2012 Apr 162012 Apr 20

Publication series

NameIEEE Symposium on Mass Storage Systems and Technologies
ISSN (Print)2160-1968

Other

Other2012 IEEE 28th Symposium on Mass Storage Systems and Technologies, MSST 2012
CountryUnited States
CityPacific Grove, CA
Period12/4/1612/4/20

Fingerprint

Flash memory
Energy utilization
Decision making
Optimal systems
Embedded systems
Simulators
Statistics
Costs
Experiments

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Jung, M., Wilson, E. H., Donofrio, D., Shalf, J., & Kandemir, M. T. (2012). NANDFlashSim: Intrinsic latency variation aware NAND flash memory system modeling and simulation at microarchitecture level. In 2012 IEEE 28th Symposium on Mass Storage Systems and Technologies, MSST 2012 [6232389] (IEEE Symposium on Mass Storage Systems and Technologies). https://doi.org/10.1109/MSST.2012.6232389
Jung, Myoungsoo ; Wilson, Ellis Herbert ; Donofrio, David ; Shalf, John ; Kandemir, Mahmut Taylan. / NANDFlashSim : Intrinsic latency variation aware NAND flash memory system modeling and simulation at microarchitecture level. 2012 IEEE 28th Symposium on Mass Storage Systems and Technologies, MSST 2012. 2012. (IEEE Symposium on Mass Storage Systems and Technologies).
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Jung, M, Wilson, EH, Donofrio, D, Shalf, J & Kandemir, MT 2012, NANDFlashSim: Intrinsic latency variation aware NAND flash memory system modeling and simulation at microarchitecture level. in 2012 IEEE 28th Symposium on Mass Storage Systems and Technologies, MSST 2012., 6232389, IEEE Symposium on Mass Storage Systems and Technologies, 2012 IEEE 28th Symposium on Mass Storage Systems and Technologies, MSST 2012, Pacific Grove, CA, United States, 12/4/16. https://doi.org/10.1109/MSST.2012.6232389

NANDFlashSim : Intrinsic latency variation aware NAND flash memory system modeling and simulation at microarchitecture level. / Jung, Myoungsoo; Wilson, Ellis Herbert; Donofrio, David; Shalf, John; Kandemir, Mahmut Taylan.

2012 IEEE 28th Symposium on Mass Storage Systems and Technologies, MSST 2012. 2012. 6232389 (IEEE Symposium on Mass Storage Systems and Technologies).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Jung M, Wilson EH, Donofrio D, Shalf J, Kandemir MT. NANDFlashSim: Intrinsic latency variation aware NAND flash memory system modeling and simulation at microarchitecture level. In 2012 IEEE 28th Symposium on Mass Storage Systems and Technologies, MSST 2012. 2012. 6232389. (IEEE Symposium on Mass Storage Systems and Technologies). https://doi.org/10.1109/MSST.2012.6232389