Two dimensional (2D) p-MoTe2 channel-based nonvolatile memory transistors with ferroelectric P(VDF-TrFE) polymer has been studied using a bottom-gate device architecture, which is introduced to dramatically reduce both of the switching and drain voltages to minimum 8 V and 10 mV, respectively. In fact, most of 2D-channel ferroelectric FETs with the same P(VDF-TrFE) polymer have used top-gate architectures, utilizing high switching pulse voltages over 20–25 V due to the existence of dead layer, which is unavoidably formed at the interface between P(VDF-TrFE) and thermal-deposited Al top gate. Key effects to realize such a low 8–13 V switching thus originate from the bottom-gate architecture. On the one hand, keys to obtain the low operation/drain voltage come from anneal-free Ohmic contact which is obtained using H2O2 solution. Thanks to the low operation voltages of 10 mV, consuming power in the nonvolatile FETs can be minimized to ~a few pW for OFF/Erase state and ~a few hundred pW for ON/Program although it eventually becomes ~nW and ~30 nW for OFF and ON states in a practical circuit operation to switch organic light emitting diodes. Our approaches of bottom-gate architecture and H2O2 contact nicely work even for transparent nonvolatile memory FET.
Bibliographical noteFunding Information:
Funding: The authors acknowledge the financial support from the National Research Foundation of Korea (NRF) (SRC program: Grant No. 2017R1A5A1014862 , vdWMRC center). J.H.P acknowledges this research was supported by Basic Science Research Program through NRF ( NRF-2019R1I1A1A01063644 ). Y.C. acknowledges this research was supported by Basic Science Research Program through NRF ( NRF-2019R1A6A3A13092041 ). S.H. acknowledges the financial support from Hyundai Motor Chung Mong-Koo Foundation .
All Science Journal Classification (ASJC) codes
- Renewable Energy, Sustainability and the Environment
- Materials Science(all)
- Electrical and Electronic Engineering