As the memory density and capacity grows, it is more likely that the number of defects increases. For this reason, in order to improve memory yield, repair analysis is widely used. Built-in redundancy analysis (BIRA) is regarded as one of the solutions to improve memory yield. However, the previous BIRA approaches require large hardware overhead to achieve an optimal repair rate. This is the main obstacle to use BIRA practically. Therefore, a new BIRA is proposed to reduce the hardware overhead significantly using spare allocation probability according to the number of faults on a sparse faulty line. The experimental results show that the hardware overhead of the proposed approach can be considerably reduced with slight loss of repair rate. Therefore, it can be used as a practical solution for BIRA.
|Title of host publication||Proceedings of the 16th International Symposium on Quality Electronic Design, ISQED 2015|
|Publisher||IEEE Computer Society|
|Number of pages||5|
|Publication status||Published - 2015 Apr 13|
|Event||16th International Symposium on Quality Electronic Design, ISQED 2015 - Santa Clara, United States|
Duration: 2015 Mar 2 → 2015 Mar 4
|Name||Proceedings - International Symposium on Quality Electronic Design, ISQED|
|Other||16th International Symposium on Quality Electronic Design, ISQED 2015|
|Period||15/3/2 → 15/3/4|
Bibliographical notePublisher Copyright:
© 2015 IEEE.
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering
- Safety, Risk, Reliability and Quality