NearZero: An integration of phase change memory with multi-core coprocessor

Myoungsoo Jung

Research output: Contribution to journalArticlepeer-review

4 Citations (Scopus)

Abstract

Multi-core based coprocessors have become powerful research vehicles to analyze a large amount of data. Even though they can accelerate data processing by using a hundred cores, the data unfortunately exist on an external storage device. The separation of computation and storage introduces redundant memory copies and unnecessary data transfers over different physical device boundaries, which limit the benefits of coprocessor-accelerated data processing. In addition, the coprocessors need assistance from host-side resources to access the external storage, which can require additional system context switches. To address these challenges, we propose NearZero, a novel DRAM-less coprocessor architecture that precisely integrates a state-of-the-art phase change memory into its multi-core accelerator. In this work, we implement an FPGA-basedmemory controller that extracts important device parameters fromreal phase changememory chips, and apply them to a commercially available hardware platformthat employs multiple processing elements over a PCIe fabric. The evaluation results reveal that NearZero achieves on average 47 percent better performance than advanced coprocessor approaches that use direct I/Os (between storage and coprocessors), while consuming only 19 percent of the total energy of such advanced coprocessors.

Original languageEnglish
Article number7902151
Pages (from-to)136-140
Number of pages5
JournalIEEE Computer Architecture Letters
Volume16
Issue number2
DOIs
Publication statusPublished - 2017 Jul 1

Bibliographical note

Funding Information:
The author thanks MemRay Corporation, Samsung, TI for their research sample donation and technical support. The author also thanks J. Zhang, H. Jeong and G. Park who help him prepare to set up preliminary evaluation environment. This research is supported by MemRay 2015-11-1731. This work is also supported in part by NRF 2016R1C1B2015312, DE-AC02-05CH 11231 and MSIP IITP- 2017-2017-0-01015.

Funding Information:
The author thanks MemRay Corporation, Samsung, TI for their research sample donation and technical support. The author also thanks J. Zhang, H. Jeong and G. Park who help him prepare to set up preliminary evaluation environment. This research is supported by MemRay 2015-11-1731. This work is also supported in part by NRF 2016R1C1B2015312, DE-AC02-05CH 11231 and MSIP IITP-2017-2017-0-01015.

Publisher Copyright:
© 2017 IEEE.

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

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