As the flash memory performance increases with more bandwidth, the flash memory channel or the interconnect is becoming a bigger bottleneck to enable high performance SSD system. However, the bandwidth of the flash memory interconnect is not increasing at the same rate as the flash memory. In addition, current flash memory bus is based on dedicated signaling where separate control signals are used for communication between the flash channel controller and the flash memory chip. In this work, we propose to exploit packetized communication to improve the effective flash memory interconnect bandwidth and propose packetized SSD (pSSD) system architecture. We first show how packetized communication can be exploited and the microarchitectural changes required. We then propose the Omnibus topology for flash memory interconnect to enable a packetized network SSD (pnSSD) among the flash memory - a 2D bus-based organization that maintains a 'bus' organization for the interconnect while enabling direct communication between the flash memory chips. The pnSSD architecture enables a new type of garbage collection that we refer to as spatial garbage collection that significantly reduces the interference between I/O requests and garbage collection. Our detailed evaluation of pnSSD shows 82% improvement in I/O latency with no garbage collection (GC) while improving I/O latency by 9.71× when GC occurs in parallel with I/O operation, through spatial garbage collection.
|Title of host publication||Proceedings - 2022 55th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2022|
|Publisher||IEEE Computer Society|
|Number of pages||16|
|Publication status||Published - 2022|
|Event||55th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2022 - Chicago, United States|
Duration: 2022 Oct 1 → 2022 Oct 5
|Name||Proceedings of the Annual International Symposium on Microarchitecture, MICRO|
|Conference||55th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2022|
|Period||22/10/1 → 22/10/5|
Bibliographical noteFunding Information:
We would like to thank the anonymous reviewers for their valuablecomments. This work was supported in part by IITP grant funded by MSIT (No. 2020-0-01303, 2020-0-01309) and in part by NRF-2020R1A2B5B0100168713.
© 2022 IEEE.
All Science Journal Classification (ASJC) codes
- Hardware and Architecture