In this paper, we propose a new adder scheme by using the redundant binary (RB) number system. In order to reduce the internal carry propagation delay time, a new P, G generation scheme, which corresponds to propagate (P) and generate (G) signals, in the redundant binary numbers has been devised. This new P, G generation scheme can lessen the probability of P, G signal occurrence, so that the carry propagation delay can be reduced. The Spice simulation results show that there is the delay time reduction in average by 15% for various test vectors, compared to the conventional normal binary (NB) adder, which can contribute to the low-power consumption. The worst case delay time for 64 b adder is estimated to be 0.6 ns under 0.25 um CMOS process at the 2.5 V supply voltage.
|Journal||Proceedings - IEEE International Symposium on Circuits and Systems|
|Publication status||Published - 2000 Jan 1|
|Event||Proceedings of the IEEE 2000 Internaitonal Symposium on Circuits and Systems - Geneva, Switz|
Duration: 2000 May 28 → 2000 May 31
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering