New design error modeling and metrics for design validation

Sungho Kang, Stephen A. Szygenda

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

When simulation is used for design verification, a subset of simulation input patterns is used, since exhaustive simulation is usually not practical. In this case, the immediate question is how much of the design has been verified? To provide a measure of the simulation pattern coverage based on design error modeling, a new simulation coverage metric is introduced. This measure is useful for obtaining insight into the actual level of design validation, since it provides more realistic results than those which are presently available.

Original languageEnglish
Title of host publicationEuropean Design Automation Conference
PublisherPubl by IEEE
Pages472-477
Number of pages6
ISBN (Print)0818627808
Publication statusPublished - 1992
EventEuropean Design Automation Conference -EURO-VHDL '92 - Hamburg, Ger
Duration: 1992 Sep 71992 Sep 10

Publication series

NameEuropean Design Automation Conference

Other

OtherEuropean Design Automation Conference -EURO-VHDL '92
CityHamburg, Ger
Period92/9/792/9/10

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this