New fast disparity estimation algorithm by diminishing search range and FPGA implementation

Jiyong Park, Wonjae Lee, Jaeseok Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents new fast disparity estimation algorithm by diminishing search range and the design of the real-time disparity estimation processor. The proposed algorithm isn't only able to reduce the computational load of disparity estimation but also the size of hardware while retaining good performance. The hardware architecture for the processor is proposed and was simulated in Verilog HDL. The processor was implemented on FPGA chip and is composed of about 180K logic gates. The disparity maps of the processor that can achieve over 60 frames per second for XGA (1024 by 768) were ranked 26th on the Middlebury stereo database with ground truth.

Original languageEnglish
Title of host publication2004 IEEE International Symposium on Consumer Electronics - Proceedings
Pages457-460
Number of pages4
Publication statusPublished - 2004 Dec 27
Event2004 IEEE International Symposium on Consumer Electronics - Proceedings - Reading, United Kingdom
Duration: 2004 Sep 12004 Sep 3

Publication series

Name2004 IEEE International Symposium on Consumer Electronics - Proceedings

Other

Other2004 IEEE International Symposium on Consumer Electronics - Proceedings
CountryUnited Kingdom
CityReading
Period04/9/104/9/3

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All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Park, J., Lee, W., & Kim, J. (2004). New fast disparity estimation algorithm by diminishing search range and FPGA implementation. In 2004 IEEE International Symposium on Consumer Electronics - Proceedings (pp. 457-460). (2004 IEEE International Symposium on Consumer Electronics - Proceedings).