This paper presents new fast disparity estimation algorithm by diminishing search range and the design of the real-time disparity estimation processor. The proposed algorithm isn't only able to reduce the computational load of disparity estimation but also the size of hardware while retaining good performance. The hardware architecture for the processor is proposed and was simulated in Verilog HDL. The processor was implemented on FPGA chip and is composed of about 180K logic gates. The disparity maps of the processor that can achieve over 60 frames per second for XGA (1024 by 768) were ranked 26th on the Middlebury stereo database with ground truth.