Abstract
The performance, power and area optimization with respect to an implementation cost is a fundamental problem in digital circuit design. With a custom design approach, finding patterns of frequent cell combinations can inspire the new cell development and optimization. A FSM (Frequent Subgraph Mining) method can help to develop new cell libraries, however, this requires huge engineering efforts for finding feasible operation conditions. This paper presents an optimized frequent subgraph mining platform by integrating various FSM methods. The experiment results with various designs demonstrate that the proposed method can reduce an overall runtime.
| Original language | English |
|---|---|
| Article number | 20171226 |
| Journal | ieice electronics express |
| Volume | 15 |
| Issue number | 9 |
| DOIs | |
| Publication status | Published - 2018 May 10 |
Bibliographical note
Funding Information:This work was supported in part by the Basic Science Research Program through the National Research Foundation of Korea by the Ministry of Education under Grant NRF-2015R1D1A1A01058856, in part by the Korea Institute for Advancement of Technology (KIAT) by the Korean Government (Motie: Ministry of Trade, Industry & Energy, HRD Program for Software-SoC Convergence) under Grant N0001883, in part by the MOTIE (Ministry of Trade, Industry & Energy (10080594) and KSRC (Korea Semiconductor Research Consortium) support program for the development of the future semiconductor device.
Publisher Copyright:
© IEICE 2018.
All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Condensed Matter Physics
- Electrical and Electronic Engineering