Abstract
This paper presents a new low power BIST TPG scheme for reducing scan transitions. It uses a transition freezing and melting method which is implemented of the transition freezing block and a MUX. When random test patterns are generated from an LFSR, transitions of those patterns satisfy pseudo-random Gaussian distribution. The proposed technique freezes transitions of patterns using a freezing value. Experimental results show that the proposed BIST TPG schemes can reduce average power reduction by about 60% without performance loss and peak power by about 30% in ISCAS'89 benchmark circuits.
| Original language | English |
|---|---|
| Pages (from-to) | 1185-1188 |
| Number of pages | 4 |
| Journal | IEICE Transactions on Information and Systems |
| Volume | E91-D |
| Issue number | 4 |
| DOIs | |
| Publication status | Published - 2008 Apr |
All Science Journal Classification (ASJC) codes
- Software
- Hardware and Architecture
- Computer Vision and Pattern Recognition
- Electrical and Electronic Engineering
- Artificial Intelligence
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Cite this
Kim, Y., Kim, K., Kim, I., Son, H., & Kang, S. (2008). New scan power reduction scheme using transition freezing for pseudo-random logic BIST. IEICE Transactions on Information and Systems, E91-D(4), 1185-1188. https://doi.org/10.1093/ietisy/e91-d.4.1185