Abstract
This paper presents a new low power BIST TPG scheme for reducing scan transitions. It uses a transition freezing and melting method which is implemented of the transition freezing block and a MUX. When random test patterns are generated from an LFSR, transitions of those patterns satisfy pseudo-random Gaussian distribution. The proposed technique freezes transitions of patterns using a freezing value. Experimental results show that the proposed BIST TPG schemes can reduce average power reduction by about 60% without performance loss and peak power by about 30% in ISCAS'89 benchmark circuits.
| Original language | English |
|---|---|
| Pages (from-to) | 1185-1188 |
| Number of pages | 4 |
| Journal | IEICE Transactions on Information and Systems |
| Volume | E91-D |
| Issue number | 4 |
| DOIs | |
| Publication status | Published - 2008 Jan 1 |
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All Science Journal Classification (ASJC) codes
- Software
- Hardware and Architecture
- Computer Vision and Pattern Recognition
- Electrical and Electronic Engineering
- Artificial Intelligence
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New scan power reduction scheme using transition freezing for pseudo-random logic BIST. / Kim, Youbean; Kim, Kicheol; Kim, Incheol; Son, Hyunwook; Kang, Sungho.
In: IEICE Transactions on Information and Systems, Vol. E91-D, No. 4, 01.01.2008, p. 1185-1188.Research output: Contribution to journal › Article
TY - JOUR
T1 - New scan power reduction scheme using transition freezing for pseudo-random logic BIST
AU - Kim, Youbean
AU - Kim, Kicheol
AU - Kim, Incheol
AU - Son, Hyunwook
AU - Kang, Sungho
PY - 2008/1/1
Y1 - 2008/1/1
N2 - This paper presents a new low power BIST TPG scheme for reducing scan transitions. It uses a transition freezing and melting method which is implemented of the transition freezing block and a MUX. When random test patterns are generated from an LFSR, transitions of those patterns satisfy pseudo-random Gaussian distribution. The proposed technique freezes transitions of patterns using a freezing value. Experimental results show that the proposed BIST TPG schemes can reduce average power reduction by about 60% without performance loss and peak power by about 30% in ISCAS'89 benchmark circuits.
AB - This paper presents a new low power BIST TPG scheme for reducing scan transitions. It uses a transition freezing and melting method which is implemented of the transition freezing block and a MUX. When random test patterns are generated from an LFSR, transitions of those patterns satisfy pseudo-random Gaussian distribution. The proposed technique freezes transitions of patterns using a freezing value. Experimental results show that the proposed BIST TPG schemes can reduce average power reduction by about 60% without performance loss and peak power by about 30% in ISCAS'89 benchmark circuits.
UR - http://www.scopus.com/inward/record.url?scp=68149170585&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=68149170585&partnerID=8YFLogxK
U2 - 10.1093/ietisy/e91-d.4.1185
DO - 10.1093/ietisy/e91-d.4.1185
M3 - Article
AN - SCOPUS:68149170585
VL - E91-D
SP - 1185
EP - 1188
JO - IEICE Transactions on Information and Systems
JF - IEICE Transactions on Information and Systems
SN - 0916-8532
IS - 4
ER -