NiO resistive random access memory nanocapacitor array on graphene

Jong Yeog Son, Young Han Shin, Hyungjun Kim, Hyun M. Jang

Research output: Contribution to journalArticle

138 Citations (Scopus)

Abstract

In this study, a NiO RRAM nanocapacitor array was fabricated on a graphene sheet, which was on a Nb-doped SrTiO3 substrate containing terraces with a regular interval of about 100 nm and an atomically smooth surface. For the formation of the NiO RRAM nanocapacitor (Pt/NiO/graphene capacitor) array, an anodic aluminum oxide (AAO) nanotemplate with a pore diameter of about 30 nm and an interpore distance of about 100 nm was used. NiO and Pt were subsequently deposited on the graphene sheet. The NiO RRAM nanocapacitor had a diameter of about 30 ± 2 nm and a thickness of about 33 ± 3 nm. Typical unipolar switching characteristics of the NiO RRAM nanocapacitor array were confirmed. The NiO RRAM nanocapacitor array on graphene exhibited lower SET and RESET voltages than that on a bare surface of Nb-doped SrTiO3.

Original languageEnglish
Pages (from-to)2655-2658
Number of pages4
JournalACS Nano
Volume4
Issue number5
DOIs
Publication statusPublished - 2010 May 25

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Graphite
random access memory
Graphene
graphene
Data storage equipment
Aluminum Oxide
capacitors
aluminum oxides
intervals
porosity
Capacitors
RRAM
electric potential
Aluminum
Oxides
Electric potential
Substrates

All Science Journal Classification (ASJC) codes

  • Materials Science(all)
  • Engineering(all)
  • Physics and Astronomy(all)

Cite this

Son, Jong Yeog ; Shin, Young Han ; Kim, Hyungjun ; Jang, Hyun M. / NiO resistive random access memory nanocapacitor array on graphene. In: ACS Nano. 2010 ; Vol. 4, No. 5. pp. 2655-2658.
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NiO resistive random access memory nanocapacitor array on graphene. / Son, Jong Yeog; Shin, Young Han; Kim, Hyungjun; Jang, Hyun M.

In: ACS Nano, Vol. 4, No. 5, 25.05.2010, p. 2655-2658.

Research output: Contribution to journalArticle

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AB - In this study, a NiO RRAM nanocapacitor array was fabricated on a graphene sheet, which was on a Nb-doped SrTiO3 substrate containing terraces with a regular interval of about 100 nm and an atomically smooth surface. For the formation of the NiO RRAM nanocapacitor (Pt/NiO/graphene capacitor) array, an anodic aluminum oxide (AAO) nanotemplate with a pore diameter of about 30 nm and an interpore distance of about 100 nm was used. NiO and Pt were subsequently deposited on the graphene sheet. The NiO RRAM nanocapacitor had a diameter of about 30 ± 2 nm and a thickness of about 33 ± 3 nm. Typical unipolar switching characteristics of the NiO RRAM nanocapacitor array were confirmed. The NiO RRAM nanocapacitor array on graphene exhibited lower SET and RESET voltages than that on a bare surface of Nb-doped SrTiO3.

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