Noise-aware interconnect power optimization in domino logic synthesis

Ki Wook Kim, Seongook Jung, Unni Narayanan, C. L. Liu, Sung Mo Kang

Research output: Contribution to journalArticle

5 Citations (Scopus)

Abstract

Realization of high-performance domino logic depends strongly on energy-efficient and noise-tolerant interconnect design in ultradeep submicrometer processes. We characterize the cycle-averaged power model for interconnects accounting for switching statistics and dynamic behaviors. For the sake of signal integrity, cross-coupling effects are also characterized, which reflect logical correlation between adjacent wires. Based on the new models for interconnect power and capacitive crosstalk, we optimize the coupling power consumed by interconnects with crosstalk constraints. Experimental results show that optimized designs save the power consumption about 14% on average.

Original languageEnglish
Pages (from-to)79-89
Number of pages11
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume11
Issue number1
DOIs
Publication statusPublished - 2003 Feb 1

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Crosstalk
Electric power utilization
Statistics
Wire
Logic Synthesis

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Kim, Ki Wook ; Jung, Seongook ; Narayanan, Unni ; Liu, C. L. ; Kang, Sung Mo. / Noise-aware interconnect power optimization in domino logic synthesis. In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2003 ; Vol. 11, No. 1. pp. 79-89.
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Noise-aware interconnect power optimization in domino logic synthesis. / Kim, Ki Wook; Jung, Seongook; Narayanan, Unni; Liu, C. L.; Kang, Sung Mo.

In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 11, No. 1, 01.02.2003, p. 79-89.

Research output: Contribution to journalArticle

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