Noise-aware power optimization for on-chip interconnect

Ki Wook Kim, Seong Ook Jung, Unni Narayanan, C. L. Liu, Sung Mo Kang

Research output: Contribution to journalConference article

5 Citations (Scopus)

Abstract

Realization of high-performance domino logic depends strongly on energy-efficient and noise-tolerant interconnect design in ultra deep sub-micron processes. We characterize the cycle-averaged power model for interconnects accounting for switching statistics and dynamic behaviors. For the sake of signal integrity, cross-coupling effects are also characterized which reflect logical correlation between adjacent wires. Based on the new models for interconnect power and capacitive crosstalk, we optimize the coupling power consumed by interconnects with crosstalk constraints. Experimental results show that optimized designs save the power consumption significantly.

Original languageEnglish
Pages (from-to)108-113
Number of pages6
JournalProceedings of the International Symposium on Low Power Electronics and Design
Publication statusPublished - 2000 Dec 3
EventProceedings of the 2000 Symposium on Low Power Electronics and Design ISLPED'00 - Portacino Coast, Italy
Duration: 2000 Jul 262000 Jul 27

Fingerprint

Crosstalk
Electric power utilization
Statistics
Wire

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

@article{95f325fb7ffc4f46952d284eb6e6f573,
title = "Noise-aware power optimization for on-chip interconnect",
abstract = "Realization of high-performance domino logic depends strongly on energy-efficient and noise-tolerant interconnect design in ultra deep sub-micron processes. We characterize the cycle-averaged power model for interconnects accounting for switching statistics and dynamic behaviors. For the sake of signal integrity, cross-coupling effects are also characterized which reflect logical correlation between adjacent wires. Based on the new models for interconnect power and capacitive crosstalk, we optimize the coupling power consumed by interconnects with crosstalk constraints. Experimental results show that optimized designs save the power consumption significantly.",
author = "Kim, {Ki Wook} and Jung, {Seong Ook} and Unni Narayanan and Liu, {C. L.} and Kang, {Sung Mo}",
year = "2000",
month = "12",
day = "3",
language = "English",
pages = "108--113",
journal = "Proceedings of the International Symposium on Low Power Electronics and Design",
issn = "1533-4678",

}

Noise-aware power optimization for on-chip interconnect. / Kim, Ki Wook; Jung, Seong Ook; Narayanan, Unni; Liu, C. L.; Kang, Sung Mo.

In: Proceedings of the International Symposium on Low Power Electronics and Design, 03.12.2000, p. 108-113.

Research output: Contribution to journalConference article

TY - JOUR

T1 - Noise-aware power optimization for on-chip interconnect

AU - Kim, Ki Wook

AU - Jung, Seong Ook

AU - Narayanan, Unni

AU - Liu, C. L.

AU - Kang, Sung Mo

PY - 2000/12/3

Y1 - 2000/12/3

N2 - Realization of high-performance domino logic depends strongly on energy-efficient and noise-tolerant interconnect design in ultra deep sub-micron processes. We characterize the cycle-averaged power model for interconnects accounting for switching statistics and dynamic behaviors. For the sake of signal integrity, cross-coupling effects are also characterized which reflect logical correlation between adjacent wires. Based on the new models for interconnect power and capacitive crosstalk, we optimize the coupling power consumed by interconnects with crosstalk constraints. Experimental results show that optimized designs save the power consumption significantly.

AB - Realization of high-performance domino logic depends strongly on energy-efficient and noise-tolerant interconnect design in ultra deep sub-micron processes. We characterize the cycle-averaged power model for interconnects accounting for switching statistics and dynamic behaviors. For the sake of signal integrity, cross-coupling effects are also characterized which reflect logical correlation between adjacent wires. Based on the new models for interconnect power and capacitive crosstalk, we optimize the coupling power consumed by interconnects with crosstalk constraints. Experimental results show that optimized designs save the power consumption significantly.

UR - http://www.scopus.com/inward/record.url?scp=0033672409&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0033672409&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:0033672409

SP - 108

EP - 113

JO - Proceedings of the International Symposium on Low Power Electronics and Design

JF - Proceedings of the International Symposium on Low Power Electronics and Design

SN - 1533-4678

ER -