Noise-aware power optimization for on-chip interconnect

Ki Wook Kim, Seong Ook Jung, Unni Narayanan, C. L. Liu, Sung Mo Kang

Research output: Contribution to conferencePaper

2 Citations (Scopus)

Abstract

Realization of high-performance domino logic depends strongly on energy-efficient and noise-tolerant interconnect design in ultra deep sub-micron processes. We characterize the cycle-averaged power model for interconnects accounting for switching statistics and dynamic behaviors. For the sake of signal integrity, cross-coupling effects are also characterized which reflect logical correlation between adjacent wires. Based on the new models for interconnect power and capacitive crosstalk, we optimize the coupling power consumed by interconnects with crosstalk constraints. Experimental results show that optimized designs save the power consumption significantly.

Original languageEnglish
Pages108-113
Number of pages6
Publication statusPublished - 2000 Jan 1
EventInternational Symposium on low Power Electronics and Design (ISLPED'2000) - Portacino Coast, Italy
Duration: 2000 Jul 262000 Jul 27

Other

OtherInternational Symposium on low Power Electronics and Design (ISLPED'2000)
CityPortacino Coast, Italy
Period00/7/2600/7/27

Fingerprint

Crosstalk
Electric power utilization
Statistics
Wire

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Kim, K. W., Jung, S. O., Narayanan, U., Liu, C. L., & Kang, S. M. (2000). Noise-aware power optimization for on-chip interconnect. 108-113. Paper presented at International Symposium on low Power Electronics and Design (ISLPED'2000), Portacino Coast, Italy, .
Kim, Ki Wook ; Jung, Seong Ook ; Narayanan, Unni ; Liu, C. L. ; Kang, Sung Mo. / Noise-aware power optimization for on-chip interconnect. Paper presented at International Symposium on low Power Electronics and Design (ISLPED'2000), Portacino Coast, Italy, .6 p.
@conference{3016fa5e8e624f729bb54b1b1ef24d9d,
title = "Noise-aware power optimization for on-chip interconnect",
abstract = "Realization of high-performance domino logic depends strongly on energy-efficient and noise-tolerant interconnect design in ultra deep sub-micron processes. We characterize the cycle-averaged power model for interconnects accounting for switching statistics and dynamic behaviors. For the sake of signal integrity, cross-coupling effects are also characterized which reflect logical correlation between adjacent wires. Based on the new models for interconnect power and capacitive crosstalk, we optimize the coupling power consumed by interconnects with crosstalk constraints. Experimental results show that optimized designs save the power consumption significantly.",
author = "Kim, {Ki Wook} and Jung, {Seong Ook} and Unni Narayanan and Liu, {C. L.} and Kang, {Sung Mo}",
year = "2000",
month = "1",
day = "1",
language = "English",
pages = "108--113",
note = "International Symposium on low Power Electronics and Design (ISLPED'2000) ; Conference date: 26-07-2000 Through 27-07-2000",

}

Kim, KW, Jung, SO, Narayanan, U, Liu, CL & Kang, SM 2000, 'Noise-aware power optimization for on-chip interconnect' Paper presented at International Symposium on low Power Electronics and Design (ISLPED'2000), Portacino Coast, Italy, 00/7/26 - 00/7/27, pp. 108-113.

Noise-aware power optimization for on-chip interconnect. / Kim, Ki Wook; Jung, Seong Ook; Narayanan, Unni; Liu, C. L.; Kang, Sung Mo.

2000. 108-113 Paper presented at International Symposium on low Power Electronics and Design (ISLPED'2000), Portacino Coast, Italy, .

Research output: Contribution to conferencePaper

TY - CONF

T1 - Noise-aware power optimization for on-chip interconnect

AU - Kim, Ki Wook

AU - Jung, Seong Ook

AU - Narayanan, Unni

AU - Liu, C. L.

AU - Kang, Sung Mo

PY - 2000/1/1

Y1 - 2000/1/1

N2 - Realization of high-performance domino logic depends strongly on energy-efficient and noise-tolerant interconnect design in ultra deep sub-micron processes. We characterize the cycle-averaged power model for interconnects accounting for switching statistics and dynamic behaviors. For the sake of signal integrity, cross-coupling effects are also characterized which reflect logical correlation between adjacent wires. Based on the new models for interconnect power and capacitive crosstalk, we optimize the coupling power consumed by interconnects with crosstalk constraints. Experimental results show that optimized designs save the power consumption significantly.

AB - Realization of high-performance domino logic depends strongly on energy-efficient and noise-tolerant interconnect design in ultra deep sub-micron processes. We characterize the cycle-averaged power model for interconnects accounting for switching statistics and dynamic behaviors. For the sake of signal integrity, cross-coupling effects are also characterized which reflect logical correlation between adjacent wires. Based on the new models for interconnect power and capacitive crosstalk, we optimize the coupling power consumed by interconnects with crosstalk constraints. Experimental results show that optimized designs save the power consumption significantly.

UR - http://www.scopus.com/inward/record.url?scp=0033651719&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0033651719&partnerID=8YFLogxK

M3 - Paper

AN - SCOPUS:0033651719

SP - 108

EP - 113

ER -

Kim KW, Jung SO, Narayanan U, Liu CL, Kang SM. Noise-aware power optimization for on-chip interconnect. 2000. Paper presented at International Symposium on low Power Electronics and Design (ISLPED'2000), Portacino Coast, Italy, .