Noise-aware power optimization for on-chip interconnect

Ki Wook Kim, Seong Ook Jung, Unni Narayanan, C. L. Liu, Sung Mo Kang

Research output: Contribution to conferencePaper

2 Citations (Scopus)

Abstract

Realization of high-performance domino logic depends strongly on energy-efficient and noise-tolerant interconnect design in ultra deep sub-micron processes. We characterize the cycle-averaged power model for interconnects accounting for switching statistics and dynamic behaviors. For the sake of signal integrity, cross-coupling effects are also characterized which reflect logical correlation between adjacent wires. Based on the new models for interconnect power and capacitive crosstalk, we optimize the coupling power consumed by interconnects with crosstalk constraints. Experimental results show that optimized designs save the power consumption significantly.

Original languageEnglish
Pages108-113
Number of pages6
Publication statusPublished - 2000
EventInternational Symposium on low Power Electronics and Design (ISLPED'2000) - Portacino Coast, Italy
Duration: 2000 Jul 262000 Jul 27

Other

OtherInternational Symposium on low Power Electronics and Design (ISLPED'2000)
CityPortacino Coast, Italy
Period00/7/2600/7/27

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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  • Cite this

    Kim, K. W., Jung, S. O., Narayanan, U., Liu, C. L., & Kang, S. M. (2000). Noise-aware power optimization for on-chip interconnect. 108-113. Paper presented at International Symposium on low Power Electronics and Design (ISLPED'2000), Portacino Coast, Italy, .