Noise constrained power optimization for dual VT domino logic

S. O. Jung, K. W. Kim, S. M. Kang

Research output: Contribution to journalConference article

3 Citations (Scopus)

Abstract

In dual threshold voltage techniques, significant subthreshold leakage current is one of the most important design problems. Specially, when dual threshold voltage is applied to the domino logic, noise immunity has to be carefully considered because the significant subthreshold current makes dynamic node much more susceptible to noise. In this paper, an analytical model for proper keeper transistor sizing to meet noise constraint is presented. Based on the same noise constraint, we propose dual threshold voltage domino logic technique to save power consumption.

Original languageEnglish
Pages (from-to)IV158-IV161
JournalMaterials Research Society Symposium - Proceedings
Volume626
Publication statusPublished - 2001
EventThermoelectric Materials 2000-The Next Generation Materials for Small-Scale Refrigeration and Power Generation Applications - San Francisco, CA, United States
Duration: 2000 Apr 242000 Apr 27

All Science Journal Classification (ASJC) codes

  • Materials Science(all)
  • Condensed Matter Physics
  • Mechanics of Materials
  • Mechanical Engineering

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