Noise-tolerant DAC BIST scheme using integral calculus approach

Hyeonuk Son, Incheol Kim, Sang Goog Lee, Jin Ho Ahn, Jeong Do Kim, Sungho Kang

Research output: Contribution to journalArticle

Abstract

This paper proposes a built-in self-test (BIST) scheme for noise-tolerant testing of a digital-to-analogue converter (DAC). The proposed BIST calculates the differences in output voltages between a DAC and test modules. These differences are used as the inputs of an integrator that determines integral nonlinearity (INL). The proposed method has an advantage of random noise cancelation and achieves a higher test accuracy than do the conventional BIST methods. The simulation results show high standard noise-immunity and fault coverage for the proposed method.

Original languageEnglish
Pages (from-to)1344-1347
Number of pages4
JournalIEICE Transactions on Electronics
VolumeE94-C
Issue number8
DOIs
Publication statusPublished - 2011 Aug

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Built-in self test
Digital to analog conversion
Testing
Electric potential

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Son, Hyeonuk ; Kim, Incheol ; Lee, Sang Goog ; Ahn, Jin Ho ; Kim, Jeong Do ; Kang, Sungho. / Noise-tolerant DAC BIST scheme using integral calculus approach. In: IEICE Transactions on Electronics. 2011 ; Vol. E94-C, No. 8. pp. 1344-1347.
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Noise-tolerant DAC BIST scheme using integral calculus approach. / Son, Hyeonuk; Kim, Incheol; Lee, Sang Goog; Ahn, Jin Ho; Kim, Jeong Do; Kang, Sungho.

In: IEICE Transactions on Electronics, Vol. E94-C, No. 8, 08.2011, p. 1344-1347.

Research output: Contribution to journalArticle

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