Non-linear library characterization method for FinFET logic cells by L1-minimization

Byung Su Kim, Hyo Sig Won, Tae Hee Han, Joon Sung Yang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

State-of-the-art process technology offers ultra-low power devices operating at ultra-low voltages. However, they show a considerable level of non-linear characteristics. Hence, the accuracy of cell delay and variation modeling for logic cells is expected to be very low with a linear interpolation. In this paper, we propose a compressive sensing based high non-linear cell delay and variation modeling. This paper introduces accuracy optimization methods to fit the delay and variation modeling by pre-processing. Pre-processing is a hybrid approach combining a linear interpolation and compressive sensing for accurate restoration with using less samples. With FinFET cell delay and variation modeling, the experimental results show that the proposed method can obtain a similar or better accuracy with a half of measurement samples than a conventional linear interpolation based modeling.

Original languageEnglish
Title of host publicationIEEE International Symposium on Circuits and Systems
Subtitle of host publicationFrom Dreams to Innovation, ISCAS 2017 - Conference Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781467368520
DOIs
Publication statusPublished - 2017 Sep 25
Event50th IEEE International Symposium on Circuits and Systems, ISCAS 2017 - Baltimore, United States
Duration: 2017 May 282017 May 31

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310

Other

Other50th IEEE International Symposium on Circuits and Systems, ISCAS 2017
CountryUnited States
CityBaltimore
Period17/5/2817/5/31

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All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Kim, B. S., Won, H. S., Han, T. H., & Yang, J. S. (2017). Non-linear library characterization method for FinFET logic cells by L1-minimization. In IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings [8050429] (Proceedings - IEEE International Symposium on Circuits and Systems). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2017.8050429