Nonvolatile ferroelectric polymer memory with controlled hierarchical nanostructures

S. J. Kang; Y. J. Park; C. Park

doi:10.1109/ISE.2011.6084959

Nonvolatile ferroelectric polymer memory with controlled hierarchical nanostructures

S. J. Kang, Y. J. Park, C. Park

Department of Materials Science and Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

In summary, we demonstrated a novel non-volatile ferroelectric polymer transistor memory operating at low voltage with reliable data retention. The nanometer scale periodic trenches of OS lamellae were prepared using block copolymer self assembly and employed as a gate insulator by hybridizing with PVDF-TrFE. Confined crystallization of PVDF-TrFE in the trenches of OS lamellae not only significantly reduces the gate leakage current but also induces effective crystal orientation that facilitates ferroelectric polarization switching. A FeFET consisting of a 1D ribbon type single crystalline TIPS-PEN as an active channel and a hybrid PVDF-TrFE/OS lamellae gate insulator exhibits I _DS hysteresis fully that is saturated at a programming voltage as low as ±8 V, ON/OFF current ratio of ∑10 ², and data retention of ∼2 hours.

Original language	English
Title of host publication	2011 - 14th International Symposium on Electrets, ISE 2011
Pages	15-16
Number of pages	2
DOIs	https://doi.org/10.1109/ISE.2011.6084959
Publication status	Published - 2011
Event	2011 IEEE 14th International Symposium on Electrets, ISE 2011 - Montpellier, France Duration: 2011 Aug 28 → 2011 Aug 31

Publication series

Name	Proceedings - International Symposium on Electrets

Other

Other	2011 IEEE 14th International Symposium on Electrets, ISE 2011
Country/Territory	France
City	Montpellier
Period	11/8/28 → 11/8/31

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering
Materials Chemistry

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10.1109/ISE.2011.6084959

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title = "Nonvolatile ferroelectric polymer memory with controlled hierarchical nanostructures",

abstract = "In summary, we demonstrated a novel non-volatile ferroelectric polymer transistor memory operating at low voltage with reliable data retention. The nanometer scale periodic trenches of OS lamellae were prepared using block copolymer self assembly and employed as a gate insulator by hybridizing with PVDF-TrFE. Confined crystallization of PVDF-TrFE in the trenches of OS lamellae not only significantly reduces the gate leakage current but also induces effective crystal orientation that facilitates ferroelectric polarization switching. A FeFET consisting of a 1D ribbon type single crystalline TIPS-PEN as an active channel and a hybrid PVDF-TrFE/OS lamellae gate insulator exhibits I DS hysteresis fully that is saturated at a programming voltage as low as ±8 V, ON/OFF current ratio of ∑10 2, and data retention of ∼2 hours.",

author = "Kang, {S. J.} and Park, {Y. J.} and C. Park",

year = "2011",

doi = "10.1109/ISE.2011.6084959",

language = "English",

isbn = "9781457710230",

series = "Proceedings - International Symposium on Electrets",

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}

Kang, SJ, Park, YJ & Park, C 2011, Nonvolatile ferroelectric polymer memory with controlled hierarchical nanostructures. in 2011 - 14th International Symposium on Electrets, ISE 2011., 6084959, Proceedings - International Symposium on Electrets, pp. 15-16, 2011 IEEE 14th International Symposium on Electrets, ISE 2011, Montpellier, France, 11/8/28. https://doi.org/10.1109/ISE.2011.6084959

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AU - Park, Y. J.

AU - Park, C.

PY - 2011

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N2 - In summary, we demonstrated a novel non-volatile ferroelectric polymer transistor memory operating at low voltage with reliable data retention. The nanometer scale periodic trenches of OS lamellae were prepared using block copolymer self assembly and employed as a gate insulator by hybridizing with PVDF-TrFE. Confined crystallization of PVDF-TrFE in the trenches of OS lamellae not only significantly reduces the gate leakage current but also induces effective crystal orientation that facilitates ferroelectric polarization switching. A FeFET consisting of a 1D ribbon type single crystalline TIPS-PEN as an active channel and a hybrid PVDF-TrFE/OS lamellae gate insulator exhibits I DS hysteresis fully that is saturated at a programming voltage as low as ±8 V, ON/OFF current ratio of ∑10 2, and data retention of ∼2 hours.

AB - In summary, we demonstrated a novel non-volatile ferroelectric polymer transistor memory operating at low voltage with reliable data retention. The nanometer scale periodic trenches of OS lamellae were prepared using block copolymer self assembly and employed as a gate insulator by hybridizing with PVDF-TrFE. Confined crystallization of PVDF-TrFE in the trenches of OS lamellae not only significantly reduces the gate leakage current but also induces effective crystal orientation that facilitates ferroelectric polarization switching. A FeFET consisting of a 1D ribbon type single crystalline TIPS-PEN as an active channel and a hybrid PVDF-TrFE/OS lamellae gate insulator exhibits I DS hysteresis fully that is saturated at a programming voltage as low as ±8 V, ON/OFF current ratio of ∑10 2, and data retention of ∼2 hours.

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M3 - Conference contribution

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Y2 - 28 August 2011 through 31 August 2011

ER -

Nonvolatile ferroelectric polymer memory with controlled hierarchical nanostructures

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