Nonvolatile ferroelectric polymer memory with controlled hierarchical nanostructures

S. J. Kang, Y. J. Park, C. Park

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In summary, we demonstrated a novel non-volatile ferroelectric polymer transistor memory operating at low voltage with reliable data retention. The nanometer scale periodic trenches of OS lamellae were prepared using block copolymer self assembly and employed as a gate insulator by hybridizing with PVDF-TrFE. Confined crystallization of PVDF-TrFE in the trenches of OS lamellae not only significantly reduces the gate leakage current but also induces effective crystal orientation that facilitates ferroelectric polarization switching. A FeFET consisting of a 1D ribbon type single crystalline TIPS-PEN as an active channel and a hybrid PVDF-TrFE/OS lamellae gate insulator exhibits I DS hysteresis fully that is saturated at a programming voltage as low as ±8 V, ON/OFF current ratio of ∑10 2, and data retention of ∼2 hours.

Original languageEnglish
Title of host publication2011 - 14th International Symposium on Electrets, ISE 2011
Pages15-16
Number of pages2
DOIs
Publication statusPublished - 2011 Dec 1
Event2011 IEEE 14th International Symposium on Electrets, ISE 2011 - Montpellier, France
Duration: 2011 Aug 282011 Aug 31

Publication series

NameProceedings - International Symposium on Electrets

Other

Other2011 IEEE 14th International Symposium on Electrets, ISE 2011
CountryFrance
CityMontpellier
Period11/8/2811/8/31

Fingerprint

lamella
Ferroelectric materials
Nanostructures
Polymers
Data storage equipment
polymers
Electric potential
Computer programming
insulators
Leakage currents
Crystal orientation
Self assembly
Block copolymers
Hysteresis
Transistors
Crystallization
Polarization
Crystalline materials
programming
block copolymers

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

Cite this

Kang, S. J., Park, Y. J., & Park, C. (2011). Nonvolatile ferroelectric polymer memory with controlled hierarchical nanostructures. In 2011 - 14th International Symposium on Electrets, ISE 2011 (pp. 15-16). [6084959] (Proceedings - International Symposium on Electrets). https://doi.org/10.1109/ISE.2011.6084959
Kang, S. J. ; Park, Y. J. ; Park, C. / Nonvolatile ferroelectric polymer memory with controlled hierarchical nanostructures. 2011 - 14th International Symposium on Electrets, ISE 2011. 2011. pp. 15-16 (Proceedings - International Symposium on Electrets).
@inproceedings{755f744a711548d3a99271fe2a1a8be5,
title = "Nonvolatile ferroelectric polymer memory with controlled hierarchical nanostructures",
abstract = "In summary, we demonstrated a novel non-volatile ferroelectric polymer transistor memory operating at low voltage with reliable data retention. The nanometer scale periodic trenches of OS lamellae were prepared using block copolymer self assembly and employed as a gate insulator by hybridizing with PVDF-TrFE. Confined crystallization of PVDF-TrFE in the trenches of OS lamellae not only significantly reduces the gate leakage current but also induces effective crystal orientation that facilitates ferroelectric polarization switching. A FeFET consisting of a 1D ribbon type single crystalline TIPS-PEN as an active channel and a hybrid PVDF-TrFE/OS lamellae gate insulator exhibits I DS hysteresis fully that is saturated at a programming voltage as low as ±8 V, ON/OFF current ratio of ∑10 2, and data retention of ∼2 hours.",
author = "Kang, {S. J.} and Park, {Y. J.} and C. Park",
year = "2011",
month = "12",
day = "1",
doi = "10.1109/ISE.2011.6084959",
language = "English",
isbn = "9781457710230",
series = "Proceedings - International Symposium on Electrets",
pages = "15--16",
booktitle = "2011 - 14th International Symposium on Electrets, ISE 2011",

}

Kang, SJ, Park, YJ & Park, C 2011, Nonvolatile ferroelectric polymer memory with controlled hierarchical nanostructures. in 2011 - 14th International Symposium on Electrets, ISE 2011., 6084959, Proceedings - International Symposium on Electrets, pp. 15-16, 2011 IEEE 14th International Symposium on Electrets, ISE 2011, Montpellier, France, 11/8/28. https://doi.org/10.1109/ISE.2011.6084959

Nonvolatile ferroelectric polymer memory with controlled hierarchical nanostructures. / Kang, S. J.; Park, Y. J.; Park, C.

2011 - 14th International Symposium on Electrets, ISE 2011. 2011. p. 15-16 6084959 (Proceedings - International Symposium on Electrets).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - Nonvolatile ferroelectric polymer memory with controlled hierarchical nanostructures

AU - Kang, S. J.

AU - Park, Y. J.

AU - Park, C.

PY - 2011/12/1

Y1 - 2011/12/1

N2 - In summary, we demonstrated a novel non-volatile ferroelectric polymer transistor memory operating at low voltage with reliable data retention. The nanometer scale periodic trenches of OS lamellae were prepared using block copolymer self assembly and employed as a gate insulator by hybridizing with PVDF-TrFE. Confined crystallization of PVDF-TrFE in the trenches of OS lamellae not only significantly reduces the gate leakage current but also induces effective crystal orientation that facilitates ferroelectric polarization switching. A FeFET consisting of a 1D ribbon type single crystalline TIPS-PEN as an active channel and a hybrid PVDF-TrFE/OS lamellae gate insulator exhibits I DS hysteresis fully that is saturated at a programming voltage as low as ±8 V, ON/OFF current ratio of ∑10 2, and data retention of ∼2 hours.

AB - In summary, we demonstrated a novel non-volatile ferroelectric polymer transistor memory operating at low voltage with reliable data retention. The nanometer scale periodic trenches of OS lamellae were prepared using block copolymer self assembly and employed as a gate insulator by hybridizing with PVDF-TrFE. Confined crystallization of PVDF-TrFE in the trenches of OS lamellae not only significantly reduces the gate leakage current but also induces effective crystal orientation that facilitates ferroelectric polarization switching. A FeFET consisting of a 1D ribbon type single crystalline TIPS-PEN as an active channel and a hybrid PVDF-TrFE/OS lamellae gate insulator exhibits I DS hysteresis fully that is saturated at a programming voltage as low as ±8 V, ON/OFF current ratio of ∑10 2, and data retention of ∼2 hours.

UR - http://www.scopus.com/inward/record.url?scp=84855275994&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84855275994&partnerID=8YFLogxK

U2 - 10.1109/ISE.2011.6084959

DO - 10.1109/ISE.2011.6084959

M3 - Conference contribution

AN - SCOPUS:84855275994

SN - 9781457710230

T3 - Proceedings - International Symposium on Electrets

SP - 15

EP - 16

BT - 2011 - 14th International Symposium on Electrets, ISE 2011

ER -

Kang SJ, Park YJ, Park C. Nonvolatile ferroelectric polymer memory with controlled hierarchical nanostructures. In 2011 - 14th International Symposium on Electrets, ISE 2011. 2011. p. 15-16. 6084959. (Proceedings - International Symposium on Electrets). https://doi.org/10.1109/ISE.2011.6084959