Nonvolatile ferroelectric polymer memory with controlled hierarchical nanostructures

S. J. Kang, Y. J. Park, C. Park

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In summary, we demonstrated a novel non-volatile ferroelectric polymer transistor memory operating at low voltage with reliable data retention. The nanometer scale periodic trenches of OS lamellae were prepared using block copolymer self assembly and employed as a gate insulator by hybridizing with PVDF-TrFE. Confined crystallization of PVDF-TrFE in the trenches of OS lamellae not only significantly reduces the gate leakage current but also induces effective crystal orientation that facilitates ferroelectric polarization switching. A FeFET consisting of a 1D ribbon type single crystalline TIPS-PEN as an active channel and a hybrid PVDF-TrFE/OS lamellae gate insulator exhibits I DS hysteresis fully that is saturated at a programming voltage as low as ±8 V, ON/OFF current ratio of ∑10 2, and data retention of ∼2 hours.

Original languageEnglish
Title of host publication2011 - 14th International Symposium on Electrets, ISE 2011
Pages15-16
Number of pages2
DOIs
Publication statusPublished - 2011
Event2011 IEEE 14th International Symposium on Electrets, ISE 2011 - Montpellier, France
Duration: 2011 Aug 282011 Aug 31

Publication series

NameProceedings - International Symposium on Electrets

Other

Other2011 IEEE 14th International Symposium on Electrets, ISE 2011
CountryFrance
CityMontpellier
Period11/8/2811/8/31

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

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