Normally-Off GaN-on-Si MISFET Using PECVD SiON Gate Dielectric

Hyun Seop Kim, Sang Woo Han, Won Ho Jang, Chun Hyung Cho, Kwang Seok Seo, Jungwoo Oh, Ho Young Cha

Research output: Contribution to journalArticle

12 Citations (Scopus)

Abstract

We have developed a silicon oxynitride (SiON) deposition process using a plasma-enhanced chemical vapor deposition system for the gate dielectric of GaN-on-Si metal-insulator-semiconductor field-effect transistors (MISFETs). The optimized SiON film had a relative dielectric constant of 5.3 and a breakdown field of 12MV/cm. A normally-off GaN-on-Si MISFET fabricated with a 33-nm SiON gate dielectric exhibited a threshold voltage of ∼2 V, an ON-resistance of 7.85Ω·cm2, and a breakdown voltage of 640 V at the OFF-state current density of 1 μA/mm. The extracted interface trap density was 1×1012 cm-2·eV-1 at Ec - Et = 0.442 eV, which resulted in negligible hysteresis and excellent dynamic characteristics.

Original languageEnglish
Article number7959555
Pages (from-to)1090-1093
Number of pages4
JournalIEEE Electron Device Letters
Volume38
Issue number8
DOIs
Publication statusPublished - 2017 Aug

Fingerprint

MISFET devices
Gate dielectrics
Silicon
Plasma enhanced chemical vapor deposition
Electric breakdown
Threshold voltage
Hysteresis
Permittivity
Current density

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Kim, H. S., Han, S. W., Jang, W. H., Cho, C. H., Seo, K. S., Oh, J., & Cha, H. Y. (2017). Normally-Off GaN-on-Si MISFET Using PECVD SiON Gate Dielectric. IEEE Electron Device Letters, 38(8), 1090-1093. [7959555]. https://doi.org/10.1109/LED.2017.2720719
Kim, Hyun Seop ; Han, Sang Woo ; Jang, Won Ho ; Cho, Chun Hyung ; Seo, Kwang Seok ; Oh, Jungwoo ; Cha, Ho Young. / Normally-Off GaN-on-Si MISFET Using PECVD SiON Gate Dielectric. In: IEEE Electron Device Letters. 2017 ; Vol. 38, No. 8. pp. 1090-1093.
@article{01f4560009e74011a8a7d59342807d3e,
title = "Normally-Off GaN-on-Si MISFET Using PECVD SiON Gate Dielectric",
abstract = "We have developed a silicon oxynitride (SiON) deposition process using a plasma-enhanced chemical vapor deposition system for the gate dielectric of GaN-on-Si metal-insulator-semiconductor field-effect transistors (MISFETs). The optimized SiON film had a relative dielectric constant of 5.3 and a breakdown field of 12MV/cm. A normally-off GaN-on-Si MISFET fabricated with a 33-nm SiON gate dielectric exhibited a threshold voltage of ∼2 V, an ON-resistance of 7.85Ω·cm2, and a breakdown voltage of 640 V at the OFF-state current density of 1 μA/mm. The extracted interface trap density was 1×1012 cm-2·eV-1 at Ec - Et = 0.442 eV, which resulted in negligible hysteresis and excellent dynamic characteristics.",
author = "Kim, {Hyun Seop} and Han, {Sang Woo} and Jang, {Won Ho} and Cho, {Chun Hyung} and Seo, {Kwang Seok} and Jungwoo Oh and Cha, {Ho Young}",
year = "2017",
month = "8",
doi = "10.1109/LED.2017.2720719",
language = "English",
volume = "38",
pages = "1090--1093",
journal = "IEEE Electron Device Letters",
issn = "0741-3106",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "8",

}

Kim, HS, Han, SW, Jang, WH, Cho, CH, Seo, KS, Oh, J & Cha, HY 2017, 'Normally-Off GaN-on-Si MISFET Using PECVD SiON Gate Dielectric', IEEE Electron Device Letters, vol. 38, no. 8, 7959555, pp. 1090-1093. https://doi.org/10.1109/LED.2017.2720719

Normally-Off GaN-on-Si MISFET Using PECVD SiON Gate Dielectric. / Kim, Hyun Seop; Han, Sang Woo; Jang, Won Ho; Cho, Chun Hyung; Seo, Kwang Seok; Oh, Jungwoo; Cha, Ho Young.

In: IEEE Electron Device Letters, Vol. 38, No. 8, 7959555, 08.2017, p. 1090-1093.

Research output: Contribution to journalArticle

TY - JOUR

T1 - Normally-Off GaN-on-Si MISFET Using PECVD SiON Gate Dielectric

AU - Kim, Hyun Seop

AU - Han, Sang Woo

AU - Jang, Won Ho

AU - Cho, Chun Hyung

AU - Seo, Kwang Seok

AU - Oh, Jungwoo

AU - Cha, Ho Young

PY - 2017/8

Y1 - 2017/8

N2 - We have developed a silicon oxynitride (SiON) deposition process using a plasma-enhanced chemical vapor deposition system for the gate dielectric of GaN-on-Si metal-insulator-semiconductor field-effect transistors (MISFETs). The optimized SiON film had a relative dielectric constant of 5.3 and a breakdown field of 12MV/cm. A normally-off GaN-on-Si MISFET fabricated with a 33-nm SiON gate dielectric exhibited a threshold voltage of ∼2 V, an ON-resistance of 7.85Ω·cm2, and a breakdown voltage of 640 V at the OFF-state current density of 1 μA/mm. The extracted interface trap density was 1×1012 cm-2·eV-1 at Ec - Et = 0.442 eV, which resulted in negligible hysteresis and excellent dynamic characteristics.

AB - We have developed a silicon oxynitride (SiON) deposition process using a plasma-enhanced chemical vapor deposition system for the gate dielectric of GaN-on-Si metal-insulator-semiconductor field-effect transistors (MISFETs). The optimized SiON film had a relative dielectric constant of 5.3 and a breakdown field of 12MV/cm. A normally-off GaN-on-Si MISFET fabricated with a 33-nm SiON gate dielectric exhibited a threshold voltage of ∼2 V, an ON-resistance of 7.85Ω·cm2, and a breakdown voltage of 640 V at the OFF-state current density of 1 μA/mm. The extracted interface trap density was 1×1012 cm-2·eV-1 at Ec - Et = 0.442 eV, which resulted in negligible hysteresis and excellent dynamic characteristics.

UR - http://www.scopus.com/inward/record.url?scp=85023751579&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85023751579&partnerID=8YFLogxK

U2 - 10.1109/LED.2017.2720719

DO - 10.1109/LED.2017.2720719

M3 - Article

AN - SCOPUS:85023751579

VL - 38

SP - 1090

EP - 1093

JO - IEEE Electron Device Letters

JF - IEEE Electron Device Letters

SN - 0741-3106

IS - 8

M1 - 7959555

ER -