NOT and NOR logic circuits using passivation dielectric involved dual gate in a-InGaZnO TFTs

Seung Hee Nam, Pyo Jin Jeon, Young Tack Lee, Syed Raza Ali Raza, Seongil Im

Research output: Contribution to journalArticle

4 Citations (Scopus)

Abstract

Dual-gate amorphous (a)-InGaZnO thin-film transistors (TFTs) are simply realized using the passivation layer of already fabricated bottom-gate TFTs as top-gate dielectric, so that an electrical biasing of either top or bottom gate may control the threshold behavior of the device. By applying a voltage to the top gate of a TFT that is serially connected to the next adjacent TFT, we could form a logic inverter with a decent voltage gain and desirable transition voltage, while a NOR logic circuit was also achieved by independent control of the dual gates. On the one hand, when both of the top and bottom gates are simultaneously controlled by single bias, our dual-gate TFT displays an excellent subthreshold swing property that leads to an excellent voltage gain in an inverter.

Original languageEnglish
Article number6644271
Pages (from-to)1527-1529
Number of pages3
JournalIEEE Electron Device Letters
Volume34
Issue number12
DOIs
Publication statusPublished - 2013 Dec 1

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All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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