Novel branch prediction strategy based on adaptive history length for high-performance microprocessor

The demands for high-performance microprocessors have recently increased. Accurate branch prediction is one of the most important factors for high-performance processors. In order to predict branch outcomes, instruction program counter bits and the history of recently executed branch outcomes are used. Among the executed branch outcomes, some histories are useful while others are useless. In addition, these useful/useless histories vary among branch instructions. Numerous studies have shown a method that identifies optimal history. However, little research has been done regarding the treatment of useless history. In this paper, a new method called Instruction Address alloyed History Length Modification branch predictor is proposed to handle the useless history bits. When PHT entries are 4,096, IAaHLM has a prediction accuracy of 93.22% and Gshare has a prediction accuracy of 91.84%.