Novel hierarchical test architecture for SOC test methodology using IEEE test standards

Dongkwan Han, Yong Lee, Sungho Kang

Research output: Contribution to journalArticlepeer-review

4 Citations (Scopus)

Abstract

SOC test methodology in ultra deep submicron (UDSM) technology with reasonable test time and cost has begun to satisfy high quality and reliability of the product. A novel hierarchical test architecture using IEEE standard 1149.1, 1149.7 and 1500 compliant facilities is proposed for the purpose of supporting flexible test environment to ensure SOC test methodology. Each embedded core in a systemon-a-chip (SOC) is controlled by test access ports (TAP) and TAP controller of IEEE standard 1149.1 as well as tested using IEEE standard 1500. An SOC device including TAPed cores is hierarchically organized by IEEE standard 1149.7 in wafer and chip level. As a result, it is possible to select/deselect all cores embedded in an SOC flexibly and reduce test cost dramatically using star scan topology.

Original languageEnglish
Pages (from-to)293-296
Number of pages4
JournalJournal of Semiconductor Technology and Science
Volume12
Issue number3
DOIs
Publication statusPublished - 2012 Sep

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'Novel hierarchical test architecture for SOC test methodology using IEEE test standards'. Together they form a unique fingerprint.

Cite this