TY - GEN
T1 - Novel Hysteresis Thresholding FPGA Architecture for Accurate Canny Edge Map
AU - Jang, Yunseok
AU - Mun, Junwon
AU - Nam, Yoojun
AU - Kim, Jaeseok
PY - 2019/6
Y1 - 2019/6
N2 - The Canny edge detector is used as a preprocessing operator in various high-level image processing techniques used in consumer electronics. Many researchers have implemented the Canny edge detector on a field-programmable gate array, which has the same hysteresis thresholding (HT) architecture. However, the use of this architecture can lead to loss of accuracy in highlevel image processing because the correct edge map cannot be obtained. In this paper, we propose a HT hardware architecture that provides the same results as the software implementation of Canny edge detection by using the idea of connected component analysis (CCA) hardware structure.
AB - The Canny edge detector is used as a preprocessing operator in various high-level image processing techniques used in consumer electronics. Many researchers have implemented the Canny edge detector on a field-programmable gate array, which has the same hysteresis thresholding (HT) architecture. However, the use of this architecture can lead to loss of accuracy in highlevel image processing because the correct edge map cannot be obtained. In this paper, we propose a HT hardware architecture that provides the same results as the software implementation of Canny edge detection by using the idea of connected component analysis (CCA) hardware structure.
UR - http://www.scopus.com/inward/record.url?scp=85071464479&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85071464479&partnerID=8YFLogxK
U2 - 10.1109/ITC-CSCC.2019.8793293
DO - 10.1109/ITC-CSCC.2019.8793293
M3 - Conference contribution
T3 - 34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019
BT - 34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019
Y2 - 23 June 2019 through 26 June 2019
ER -