Novel Hysteresis Thresholding FPGA Architecture for Accurate Canny Edge Map

Yunseok Jang, Junwon Mun, Yoojun Nam, Jaeseok Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The Canny edge detector is used as a preprocessing operator in various high-level image processing techniques used in consumer electronics. Many researchers have implemented the Canny edge detector on a field-programmable gate array, which has the same hysteresis thresholding (HT) architecture. However, the use of this architecture can lead to loss of accuracy in highlevel image processing because the correct edge map cannot be obtained. In this paper, we propose a HT hardware architecture that provides the same results as the software implementation of Canny edge detection by using the idea of connected component analysis (CCA) hardware structure.

Original languageEnglish
Title of host publication34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728132716
DOIs
Publication statusPublished - 2019 Jun
Event34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019 - JeJu, Korea, Republic of
Duration: 2019 Jun 232019 Jun 26

Publication series

Name34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019

Conference

Conference34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019
CountryKorea, Republic of
CityJeJu
Period19/6/2319/6/26

Fingerprint

Hysteresis
Field programmable gate arrays (FPGA)
Image processing
Detectors
Hardware
Consumer electronics
Edge detection

All Science Journal Classification (ASJC) codes

  • Information Systems
  • Electrical and Electronic Engineering
  • Artificial Intelligence
  • Computer Networks and Communications
  • Hardware and Architecture

Cite this

Jang, Y., Mun, J., Nam, Y., & Kim, J. (2019). Novel Hysteresis Thresholding FPGA Architecture for Accurate Canny Edge Map. In 34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019 [8793293] (34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ITC-CSCC.2019.8793293
Jang, Yunseok ; Mun, Junwon ; Nam, Yoojun ; Kim, Jaeseok. / Novel Hysteresis Thresholding FPGA Architecture for Accurate Canny Edge Map. 34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019. Institute of Electrical and Electronics Engineers Inc., 2019. (34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019).
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abstract = "The Canny edge detector is used as a preprocessing operator in various high-level image processing techniques used in consumer electronics. Many researchers have implemented the Canny edge detector on a field-programmable gate array, which has the same hysteresis thresholding (HT) architecture. However, the use of this architecture can lead to loss of accuracy in highlevel image processing because the correct edge map cannot be obtained. In this paper, we propose a HT hardware architecture that provides the same results as the software implementation of Canny edge detection by using the idea of connected component analysis (CCA) hardware structure.",
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Jang, Y, Mun, J, Nam, Y & Kim, J 2019, Novel Hysteresis Thresholding FPGA Architecture for Accurate Canny Edge Map. in 34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019., 8793293, 34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019, Institute of Electrical and Electronics Engineers Inc., 34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019, JeJu, Korea, Republic of, 19/6/23. https://doi.org/10.1109/ITC-CSCC.2019.8793293

Novel Hysteresis Thresholding FPGA Architecture for Accurate Canny Edge Map. / Jang, Yunseok; Mun, Junwon; Nam, Yoojun; Kim, Jaeseok.

34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019. Institute of Electrical and Electronics Engineers Inc., 2019. 8793293 (34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Jang Y, Mun J, Nam Y, Kim J. Novel Hysteresis Thresholding FPGA Architecture for Accurate Canny Edge Map. In 34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019. Institute of Electrical and Electronics Engineers Inc. 2019. 8793293. (34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019). https://doi.org/10.1109/ITC-CSCC.2019.8793293