Novel Hysteresis Thresholding FPGA Architecture for Accurate Canny Edge Map

Yunseok Jang; Junwon Mun; Yoojun Nam; Jaeseok Kim

doi:10.1109/ITC-CSCC.2019.8793293

Novel Hysteresis Thresholding FPGA Architecture for Accurate Canny Edge Map

Yunseok Jang, Junwon Mun, Yoojun Nam, Jaeseok Kim

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

The Canny edge detector is used as a preprocessing operator in various high-level image processing techniques used in consumer electronics. Many researchers have implemented the Canny edge detector on a field-programmable gate array, which has the same hysteresis thresholding (HT) architecture. However, the use of this architecture can lead to loss of accuracy in highlevel image processing because the correct edge map cannot be obtained. In this paper, we propose a HT hardware architecture that provides the same results as the software implementation of Canny edge detection by using the idea of connected component analysis (CCA) hardware structure.

Original language	English
Title of host publication	34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728132716
DOIs	https://doi.org/10.1109/ITC-CSCC.2019.8793293
Publication status	Published - 2019 Jun
Event	34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019 - JeJu, Korea, Republic of Duration: 2019 Jun 23 → 2019 Jun 26

Publication series

Name	34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019

Conference

Conference	34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019
Country	Korea, Republic of
City	JeJu
Period	19/6/23 → 19/6/26

All Science Journal Classification (ASJC) codes

Information Systems
Electrical and Electronic Engineering
Artificial Intelligence
Computer Networks and Communications
Hardware and Architecture

Access to Document

10.1109/ITC-CSCC.2019.8793293

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Jang, Y., Mun, J., Nam, Y., & Kim, J. (2019). Novel Hysteresis Thresholding FPGA Architecture for Accurate Canny Edge Map. In 34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019 [8793293] (34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ITC-CSCC.2019.8793293

Jang, Yunseok ; Mun, Junwon ; Nam, Yoojun ; Kim, Jaeseok. / Novel Hysteresis Thresholding FPGA Architecture for Accurate Canny Edge Map. 34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019. Institute of Electrical and Electronics Engineers Inc., 2019. (34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019).

@inproceedings{03dc86fe394349e0868fc80d91410036,

title = "Novel Hysteresis Thresholding FPGA Architecture for Accurate Canny Edge Map",

abstract = "The Canny edge detector is used as a preprocessing operator in various high-level image processing techniques used in consumer electronics. Many researchers have implemented the Canny edge detector on a field-programmable gate array, which has the same hysteresis thresholding (HT) architecture. However, the use of this architecture can lead to loss of accuracy in highlevel image processing because the correct edge map cannot be obtained. In this paper, we propose a HT hardware architecture that provides the same results as the software implementation of Canny edge detection by using the idea of connected component analysis (CCA) hardware structure.",

author = "Yunseok Jang and Junwon Mun and Yoojun Nam and Jaeseok Kim",

year = "2019",

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series = "34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019",

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note = "34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019 ; Conference date: 23-06-2019 Through 26-06-2019",

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Jang, Y, Mun, J, Nam, Y & Kim, J 2019, Novel Hysteresis Thresholding FPGA Architecture for Accurate Canny Edge Map. in 34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019., 8793293, 34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019, Institute of Electrical and Electronics Engineers Inc., 34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019, JeJu, Korea, Republic of, 19/6/23. https://doi.org/10.1109/ITC-CSCC.2019.8793293

Novel Hysteresis Thresholding FPGA Architecture for Accurate Canny Edge Map. / Jang, Yunseok; Mun, Junwon; Nam, Yoojun; Kim, Jaeseok.

34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019. Institute of Electrical and Electronics Engineers Inc., 2019. 8793293 (34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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N2 - The Canny edge detector is used as a preprocessing operator in various high-level image processing techniques used in consumer electronics. Many researchers have implemented the Canny edge detector on a field-programmable gate array, which has the same hysteresis thresholding (HT) architecture. However, the use of this architecture can lead to loss of accuracy in highlevel image processing because the correct edge map cannot be obtained. In this paper, we propose a HT hardware architecture that provides the same results as the software implementation of Canny edge detection by using the idea of connected component analysis (CCA) hardware structure.

AB - The Canny edge detector is used as a preprocessing operator in various high-level image processing techniques used in consumer electronics. Many researchers have implemented the Canny edge detector on a field-programmable gate array, which has the same hysteresis thresholding (HT) architecture. However, the use of this architecture can lead to loss of accuracy in highlevel image processing because the correct edge map cannot be obtained. In this paper, we propose a HT hardware architecture that provides the same results as the software implementation of Canny edge detection by using the idea of connected component analysis (CCA) hardware structure.

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Jang Y, Mun J, Nam Y, Kim J. Novel Hysteresis Thresholding FPGA Architecture for Accurate Canny Edge Map. In 34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019. Institute of Electrical and Electronics Engineers Inc. 2019. 8793293. (34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019). https://doi.org/10.1109/ITC-CSCC.2019.8793293