This paper describes a method to numerically calculate the design margin and to estimate the yield associated with the read access failure for sub-100-nm SRAM. Process variations at sub-100 nm not only affect SRAM cells but also periphery circuits, such as the sense amplifier (SA) and the tracking scheme. Simulation that incorporates both SRAM cells and surrounding circuits is either accurate but computationally expensive (comprehensive Monte Carlo simulation), or overly simple (fixed corner design) and unable to capture crucial statistical variation concern, dominant in sub-100-nm designs. By mathematically combining the separate Monte Carlo simulation results of SRAM cells and each peripheral block, we show that the distribution of the SA input voltage can be estimated accurately in a case where fixed corner simulation underestimates by 19%. We also present the yield equation by combining the SA input voltage and the SA offset distribution, which can be used to choose the design point. In addition, yield sensitivities are derived from the yield data to make sure that the yield has good dependence to design variables.
|Number of pages||5|
|Journal||IEEE Transactions on Circuits and Systems II: Express Briefs|
|Publication status||Published - 2008|
Bibliographical noteFunding Information:
Manuscript received December 19, 2007; revised March 1, 2008. First published May 23, 2008; current version published September 12, 2008. This work was supported in part by the Ministry of Information and Communication (MIC), Korea, under the Information Technology Research Center (ITRC) support program supervised by the Institute for Information Technology Advancement (IITA) under Grant IITA-2008-(C1090-0801-0012). This paper was recommended by Associate Editor M. Anis.
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering