Off-chip test architecture for improving multi-site testing efficiency using tri-state decoder and 3V-level encoder

Sungyoul Seo, Hyeonchan Lim, Soyeon Kang, Sungho Kang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Over recent generations, multi-site testing became the trend in the semiconductor test technology. According to this trend, the solution using low-end automatic test equipment (ATE) and built off self-test (BOST) have been extensively researched in the field of memory test and logic test. Despite the success in the memory test, the logic test still has to solve some problems such as test pin counts, test data volume, etc. In this paper, we present a new off-chip test architecture for improving multi-site testing efficiency, which is composed of tri-state decoders and 3V-level encoders. It is useful to improve total test application time (TAT) by reducing the test pin counts and the test data volume. Moreover, this off-chip is easily compatible with the existing scan compression method. Experimental results show that this test architecture improves the multi-site testing efficiency through reducing TAT by 20% on both International Symposium on Circuits and Systems (ISCAS)'89 and large International Test Conference (ITC)'99 benchmark circuits in all of cases compared to the previous works.

Original languageEnglish
Title of host publicationProceedings of the 18th International Symposium on Quality Electronic Design, ISQED 2017
PublisherIEEE Computer Society
Pages191-195
Number of pages5
ISBN (Electronic)9781509054046
DOIs
Publication statusPublished - 2017 May 2
Event18th International Symposium on Quality Electronic Design, ISQED 2017 - Santa Clara, United States
Duration: 2017 Mar 142017 Mar 15

Publication series

NameProceedings - International Symposium on Quality Electronic Design, ISQED
ISSN (Print)1948-3287
ISSN (Electronic)1948-3295

Other

Other18th International Symposium on Quality Electronic Design, ISQED 2017
CountryUnited States
CitySanta Clara
Period17/3/1417/3/15

Fingerprint

Testing
Data storage equipment
Networks (circuits)
Semiconductor materials

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

Cite this

Seo, S., Lim, H., Kang, S., & Kang, S. (2017). Off-chip test architecture for improving multi-site testing efficiency using tri-state decoder and 3V-level encoder. In Proceedings of the 18th International Symposium on Quality Electronic Design, ISQED 2017 (pp. 191-195). [7918315] (Proceedings - International Symposium on Quality Electronic Design, ISQED). IEEE Computer Society. https://doi.org/10.1109/ISQED.2017.7918315
Seo, Sungyoul ; Lim, Hyeonchan ; Kang, Soyeon ; Kang, Sungho. / Off-chip test architecture for improving multi-site testing efficiency using tri-state decoder and 3V-level encoder. Proceedings of the 18th International Symposium on Quality Electronic Design, ISQED 2017. IEEE Computer Society, 2017. pp. 191-195 (Proceedings - International Symposium on Quality Electronic Design, ISQED).
@inproceedings{2a41aa61c5a84dfa85838376c1adab8d,
title = "Off-chip test architecture for improving multi-site testing efficiency using tri-state decoder and 3V-level encoder",
abstract = "Over recent generations, multi-site testing became the trend in the semiconductor test technology. According to this trend, the solution using low-end automatic test equipment (ATE) and built off self-test (BOST) have been extensively researched in the field of memory test and logic test. Despite the success in the memory test, the logic test still has to solve some problems such as test pin counts, test data volume, etc. In this paper, we present a new off-chip test architecture for improving multi-site testing efficiency, which is composed of tri-state decoders and 3V-level encoders. It is useful to improve total test application time (TAT) by reducing the test pin counts and the test data volume. Moreover, this off-chip is easily compatible with the existing scan compression method. Experimental results show that this test architecture improves the multi-site testing efficiency through reducing TAT by 20{\%} on both International Symposium on Circuits and Systems (ISCAS)'89 and large International Test Conference (ITC)'99 benchmark circuits in all of cases compared to the previous works.",
author = "Sungyoul Seo and Hyeonchan Lim and Soyeon Kang and Sungho Kang",
year = "2017",
month = "5",
day = "2",
doi = "10.1109/ISQED.2017.7918315",
language = "English",
series = "Proceedings - International Symposium on Quality Electronic Design, ISQED",
publisher = "IEEE Computer Society",
pages = "191--195",
booktitle = "Proceedings of the 18th International Symposium on Quality Electronic Design, ISQED 2017",
address = "United States",

}

Seo, S, Lim, H, Kang, S & Kang, S 2017, Off-chip test architecture for improving multi-site testing efficiency using tri-state decoder and 3V-level encoder. in Proceedings of the 18th International Symposium on Quality Electronic Design, ISQED 2017., 7918315, Proceedings - International Symposium on Quality Electronic Design, ISQED, IEEE Computer Society, pp. 191-195, 18th International Symposium on Quality Electronic Design, ISQED 2017, Santa Clara, United States, 17/3/14. https://doi.org/10.1109/ISQED.2017.7918315

Off-chip test architecture for improving multi-site testing efficiency using tri-state decoder and 3V-level encoder. / Seo, Sungyoul; Lim, Hyeonchan; Kang, Soyeon; Kang, Sungho.

Proceedings of the 18th International Symposium on Quality Electronic Design, ISQED 2017. IEEE Computer Society, 2017. p. 191-195 7918315 (Proceedings - International Symposium on Quality Electronic Design, ISQED).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - Off-chip test architecture for improving multi-site testing efficiency using tri-state decoder and 3V-level encoder

AU - Seo, Sungyoul

AU - Lim, Hyeonchan

AU - Kang, Soyeon

AU - Kang, Sungho

PY - 2017/5/2

Y1 - 2017/5/2

N2 - Over recent generations, multi-site testing became the trend in the semiconductor test technology. According to this trend, the solution using low-end automatic test equipment (ATE) and built off self-test (BOST) have been extensively researched in the field of memory test and logic test. Despite the success in the memory test, the logic test still has to solve some problems such as test pin counts, test data volume, etc. In this paper, we present a new off-chip test architecture for improving multi-site testing efficiency, which is composed of tri-state decoders and 3V-level encoders. It is useful to improve total test application time (TAT) by reducing the test pin counts and the test data volume. Moreover, this off-chip is easily compatible with the existing scan compression method. Experimental results show that this test architecture improves the multi-site testing efficiency through reducing TAT by 20% on both International Symposium on Circuits and Systems (ISCAS)'89 and large International Test Conference (ITC)'99 benchmark circuits in all of cases compared to the previous works.

AB - Over recent generations, multi-site testing became the trend in the semiconductor test technology. According to this trend, the solution using low-end automatic test equipment (ATE) and built off self-test (BOST) have been extensively researched in the field of memory test and logic test. Despite the success in the memory test, the logic test still has to solve some problems such as test pin counts, test data volume, etc. In this paper, we present a new off-chip test architecture for improving multi-site testing efficiency, which is composed of tri-state decoders and 3V-level encoders. It is useful to improve total test application time (TAT) by reducing the test pin counts and the test data volume. Moreover, this off-chip is easily compatible with the existing scan compression method. Experimental results show that this test architecture improves the multi-site testing efficiency through reducing TAT by 20% on both International Symposium on Circuits and Systems (ISCAS)'89 and large International Test Conference (ITC)'99 benchmark circuits in all of cases compared to the previous works.

UR - http://www.scopus.com/inward/record.url?scp=85019646164&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85019646164&partnerID=8YFLogxK

U2 - 10.1109/ISQED.2017.7918315

DO - 10.1109/ISQED.2017.7918315

M3 - Conference contribution

AN - SCOPUS:85019646164

T3 - Proceedings - International Symposium on Quality Electronic Design, ISQED

SP - 191

EP - 195

BT - Proceedings of the 18th International Symposium on Quality Electronic Design, ISQED 2017

PB - IEEE Computer Society

ER -

Seo S, Lim H, Kang S, Kang S. Off-chip test architecture for improving multi-site testing efficiency using tri-state decoder and 3V-level encoder. In Proceedings of the 18th International Symposium on Quality Electronic Design, ISQED 2017. IEEE Computer Society. 2017. p. 191-195. 7918315. (Proceedings - International Symposium on Quality Electronic Design, ISQED). https://doi.org/10.1109/ISQED.2017.7918315