Over recent generations, multi-site testing became the trend in the semiconductor test technology. According to this trend, the solution using low-end automatic test equipment (ATE) and built off self-test (BOST) have been extensively researched in the field of memory test and logic test. Despite the success in the memory test, the logic test still has to solve some problems such as test pin counts, test data volume, etc. In this paper, we present a new off-chip test architecture for improving multi-site testing efficiency, which is composed of tri-state decoders and 3V-level encoders. It is useful to improve total test application time (TAT) by reducing the test pin counts and the test data volume. Moreover, this off-chip is easily compatible with the existing scan compression method. Experimental results show that this test architecture improves the multi-site testing efficiency through reducing TAT by 20% on both International Symposium on Circuits and Systems (ISCAS)'89 and large International Test Conference (ITC)'99 benchmark circuits in all of cases compared to the previous works.
|Title of host publication||Proceedings of the 18th International Symposium on Quality Electronic Design, ISQED 2017|
|Publisher||IEEE Computer Society|
|Number of pages||5|
|Publication status||Published - 2017 May 2|
|Event||18th International Symposium on Quality Electronic Design, ISQED 2017 - Santa Clara, United States|
Duration: 2017 Mar 14 → 2017 Mar 15
|Name||Proceedings - International Symposium on Quality Electronic Design, ISQED|
|Other||18th International Symposium on Quality Electronic Design, ISQED 2017|
|Period||17/3/14 → 17/3/15|
Bibliographical noteFunding Information:
This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government(MSIP) (No. 2015R1A2A1A13001751).
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering
- Safety, Risk, Reliability and Quality