This paper presents a feasibility analysis to predict the optimal size of VLSI CNN implementations. A 3×3 CNN IC test prototype was designed and fabricated for this purpose. The study considers both the manufacturability and computing performance power of hypothetical large CNN arrays. The manufacturability analysis has been geared towards IC yield prediction using our actual IC layout along with some realistic parameters representing the 'cleanliness' of the manufacturing line. Additionally, from experimental results we have found that offset effects are dominant and if they are not properly canceled they can produce incorrect processing results. As a one-on-one mapping between image pixels and CNN cells is practically impossible, the computing performance analysis concentrates on the optimal array size needed to efficiently implement a multiplexing scheme versus the hypothetical fully parallel CNN architecture. Our results indicate that a 50×50 array is feasible for a time multiplexing scheme. This array will consume around 4W. The predicted yield of such array is about 70%. The implementation cost is around 30% of a 100×100 array, or alternatively only 2% of a 200×200 array, and only 0.04% slower than a hypothetical fully parallel processing architecture.
|Number of pages||6|
|Publication status||Published - 1996 Dec 1|
|Event||Proceedings of the 1996 4th IEEE International Workshop on Cellular Neural Networks, and Their Applications, CNNA-96 - Seville, Spain|
Duration: 1996 Jun 24 → 1996 Jun 26
|Other||Proceedings of the 1996 4th IEEE International Workshop on Cellular Neural Networks, and Their Applications, CNNA-96|
|Period||96/6/24 → 96/6/26|
All Science Journal Classification (ASJC) codes