@inproceedings{c63931bd05174da29b7c8041873e8c94,
title = "Optimal timing for skew-tolerant high-speed domino logic",
abstract = "When low threshold voltage (Vt) is applied to domino logic to improve the performance, the tradeoff between performance and noise margin is a major design issue. To resolve the tradeoff we propose Skew-Tolerant High-Speed (STHS) domino logic, which incorporates a dual keeper structure and delay logic gates. Detailed timing analysis of STHS domino logic induces optimal timing conditions wherein contention-free skew-tolerant window is maximized. We show that dual keeper structure increases innate noise-tolerance, and clock delay control logic fortifies signal skew-tolerance. Simulation results show that STHS domino logic is more robust to noise and signal skew than High-Speed (HS) domino logic, while presenting better performance and power efficiency.",
author = "Jung, {Seong Ook} and Kim, {Ki Wook} and Kang, {Sung Mo}",
note = "Publisher Copyright: {\textcopyright} 2002 IEEE. Copyright: Copyright 2015 Elsevier B.V., All rights reserved.; IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2002 ; Conference date: 25-04-2002 Through 26-04-2002",
year = "2002",
doi = "10.1109/ISVLSI.2002.1016871",
language = "English",
series = "Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI",
publisher = "IEEE Computer Society",
pages = "41--46",
editor = "Asim Smailagic and Robert Brodersen",
booktitle = "Proceedings - IEEE Computer Society Annual Symposium on VLSI",
address = "United States",
}