Optimal timing for skew-tolerant high-speed domino logic

Seong Ook Jung; Ki Wook Kim; Sung Mo Kang

doi:10.1109/ISVLSI.2002.1016871

Optimal timing for skew-tolerant high-speed domino logic

Seong Ook Jung, Ki Wook Kim, Sung Mo Kang

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

When low threshold voltage (V_t) is applied to domino logic to improve the performance, the tradeoff between performance and noise margin is a major design issue. To resolve the tradeoff we propose Skew-Tolerant High-Speed (STHS) domino logic, which incorporates a dual keeper structure and delay logic gates. Detailed timing analysis of STHS domino logic induces optimal timing conditions wherein contention-free skew-tolerant window is maximized. We show that dual keeper structure increases innate noise-tolerance, and clock delay control logic fortifies signal skew-tolerance. Simulation results show that STHS domino logic is more robust to noise and signal skew than High-Speed (HS) domino logic, while presenting better performance and power efficiency.

Original language	English
Title of host publication	Proceedings - IEEE Computer Society Annual Symposium on VLSI
Subtitle of host publication	New Paradigms for VLSI Systems Design, ISVLSI 2002
Editors	Asim Smailagic, Robert Brodersen
Publisher	IEEE Computer Society
Pages	41-46
Number of pages	6
ISBN (Electronic)	0769514863
DOIs	https://doi.org/10.1109/ISVLSI.2002.1016871
Publication status	Published - 2002
Event	IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2002 - Pittsburgh, United States Duration: 2002 Apr 25 → 2002 Apr 26

Publication series

Name	Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
Volume	2002-January
ISSN (Print)	2159-3469
ISSN (Electronic)	2159-3477

Other

Other	IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2002
Country	United States
City	Pittsburgh
Period	02/4/25 → 02/4/26

Bibliographical note

Publisher Copyright:
© 2002 IEEE.

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Control and Systems Engineering
Electrical and Electronic Engineering

Access to Document

10.1109/ISVLSI.2002.1016871

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Jung, S. O., Kim, K. W., & Kang, S. M. (2002). Optimal timing for skew-tolerant high-speed domino logic. In A. Smailagic, & R. Brodersen (Eds.), Proceedings - IEEE Computer Society Annual Symposium on VLSI: New Paradigms for VLSI Systems Design, ISVLSI 2002 (pp. 41-46). [1016871] (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI; Vol. 2002-January). IEEE Computer Society. https://doi.org/10.1109/ISVLSI.2002.1016871

Jung, Seong Ook ; Kim, Ki Wook ; Kang, Sung Mo. / Optimal timing for skew-tolerant high-speed domino logic. Proceedings - IEEE Computer Society Annual Symposium on VLSI: New Paradigms for VLSI Systems Design, ISVLSI 2002. editor / Asim Smailagic ; Robert Brodersen. IEEE Computer Society, 2002. pp. 41-46 (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI).

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title = "Optimal timing for skew-tolerant high-speed domino logic",

abstract = "When low threshold voltage (Vt) is applied to domino logic to improve the performance, the tradeoff between performance and noise margin is a major design issue. To resolve the tradeoff we propose Skew-Tolerant High-Speed (STHS) domino logic, which incorporates a dual keeper structure and delay logic gates. Detailed timing analysis of STHS domino logic induces optimal timing conditions wherein contention-free skew-tolerant window is maximized. We show that dual keeper structure increases innate noise-tolerance, and clock delay control logic fortifies signal skew-tolerance. Simulation results show that STHS domino logic is more robust to noise and signal skew than High-Speed (HS) domino logic, while presenting better performance and power efficiency.",

author = "Jung, {Seong Ook} and Kim, {Ki Wook} and Kang, {Sung Mo}",

note = "Publisher Copyright: {\textcopyright} 2002 IEEE.; IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2002 ; Conference date: 25-04-2002 Through 26-04-2002",

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doi = "10.1109/ISVLSI.2002.1016871",

language = "English",

series = "Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI",

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Jung, SO, Kim, KW & Kang, SM 2002, Optimal timing for skew-tolerant high-speed domino logic. in A Smailagic & R Brodersen (eds), Proceedings - IEEE Computer Society Annual Symposium on VLSI: New Paradigms for VLSI Systems Design, ISVLSI 2002., 1016871, Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI, vol. 2002-January, IEEE Computer Society, pp. 41-46, IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2002, Pittsburgh, United States, 02/4/25. https://doi.org/10.1109/ISVLSI.2002.1016871

Optimal timing for skew-tolerant high-speed domino logic. / Jung, Seong Ook; Kim, Ki Wook; Kang, Sung Mo.

Proceedings - IEEE Computer Society Annual Symposium on VLSI: New Paradigms for VLSI Systems Design, ISVLSI 2002. ed. / Asim Smailagic; Robert Brodersen. IEEE Computer Society, 2002. p. 41-46 1016871 (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI; Vol. 2002-January).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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N2 - When low threshold voltage (Vt) is applied to domino logic to improve the performance, the tradeoff between performance and noise margin is a major design issue. To resolve the tradeoff we propose Skew-Tolerant High-Speed (STHS) domino logic, which incorporates a dual keeper structure and delay logic gates. Detailed timing analysis of STHS domino logic induces optimal timing conditions wherein contention-free skew-tolerant window is maximized. We show that dual keeper structure increases innate noise-tolerance, and clock delay control logic fortifies signal skew-tolerance. Simulation results show that STHS domino logic is more robust to noise and signal skew than High-Speed (HS) domino logic, while presenting better performance and power efficiency.

AB - When low threshold voltage (Vt) is applied to domino logic to improve the performance, the tradeoff between performance and noise margin is a major design issue. To resolve the tradeoff we propose Skew-Tolerant High-Speed (STHS) domino logic, which incorporates a dual keeper structure and delay logic gates. Detailed timing analysis of STHS domino logic induces optimal timing conditions wherein contention-free skew-tolerant window is maximized. We show that dual keeper structure increases innate noise-tolerance, and clock delay control logic fortifies signal skew-tolerance. Simulation results show that STHS domino logic is more robust to noise and signal skew than High-Speed (HS) domino logic, while presenting better performance and power efficiency.

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Jung SO, Kim KW, Kang SM. Optimal timing for skew-tolerant high-speed domino logic. In Smailagic A, Brodersen R, editors, Proceedings - IEEE Computer Society Annual Symposium on VLSI: New Paradigms for VLSI Systems Design, ISVLSI 2002. IEEE Computer Society. 2002. p. 41-46. 1016871. (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI). https://doi.org/10.1109/ISVLSI.2002.1016871

Optimal timing for skew-tolerant high-speed domino logic

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