Parallel BIST architecture for CAMs

Yong Seok Kang, Jong Cheol Lee, Sungho Kang

Research output: Contribution to journalArticlepeer-review

20 Citations (Scopus)


A new parallel test algorithm and a built-in self test (BIST) architecture for efficient testing of various types of functional faults in content addressable memories (CAMs) are developed. The results show that efficient and practical testing with very low complexity and area overhead can be achieved.

Original languageEnglish
Pages (from-to)30-31
Number of pages2
JournalElectronics Letters
Issue number1
Publication statusPublished - 1997 Jan 2

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering


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