A new parallel test algorithm and a built-in self test (BIST) architecture for efficient testing of various types of functional faults in content addressable memories (CAMs) are developed. The results show that efficient and practical testing with very low complexity and area overhead can be achieved.
|Number of pages||2|
|Publication status||Published - 1997 Jan 2|
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering