Parallel BIST architecture for CAMs

Yong Seok Kang; Jong Cheol Lee; Sungho Kang

doi:10.1049/el:19970020

Parallel BIST architecture for CAMs

Yong Seok Kang, Jong Cheol Lee, Sungho Kang

Department of Electrical and Electronic Engineering

Research output: Contribution to journal › Article › peer-review

20 Citations (Scopus)

Abstract

A new parallel test algorithm and a built-in self test (BIST) architecture for efficient testing of various types of functional faults in content addressable memories (CAMs) are developed. The results show that efficient and practical testing with very low complexity and area overhead can be achieved.

Original language	English
Pages (from-to)	30-31
Number of pages	2
Journal	Electronics Letters
Volume	33
Issue number	1
DOIs	https://doi.org/10.1049/el:19970020
Publication status	Published - 1997 Jan 2

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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10.1049/el:19970020

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@article{63f4065e63f84c41a32ed9aa607daab7,

title = "Parallel BIST architecture for CAMs",

abstract = "A new parallel test algorithm and a built-in self test (BIST) architecture for efficient testing of various types of functional faults in content addressable memories (CAMs) are developed. The results show that efficient and practical testing with very low complexity and area overhead can be achieved.",

author = "Kang, {Yong Seok} and Lee, {Jong Cheol} and Sungho Kang",

year = "1997",

month = jan,

day = "2",

doi = "10.1049/el:19970020",

language = "English",

volume = "33",

pages = "30--31",

journal = "Electronics Letters",

issn = "0013-5194",

publisher = "Institution of Engineering and Technology",

number = "1",

}

TY - JOUR

T1 - Parallel BIST architecture for CAMs

AU - Kang, Yong Seok

AU - Lee, Jong Cheol

AU - Kang, Sungho

PY - 1997/1/2

Y1 - 1997/1/2

N2 - A new parallel test algorithm and a built-in self test (BIST) architecture for efficient testing of various types of functional faults in content addressable memories (CAMs) are developed. The results show that efficient and practical testing with very low complexity and area overhead can be achieved.

AB - A new parallel test algorithm and a built-in self test (BIST) architecture for efficient testing of various types of functional faults in content addressable memories (CAMs) are developed. The results show that efficient and practical testing with very low complexity and area overhead can be achieved.

UR - http://www.scopus.com/inward/record.url?scp=0031546305&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0031546305&partnerID=8YFLogxK

U2 - 10.1049/el:19970020

DO - 10.1049/el:19970020

M3 - Article

AN - SCOPUS:0031546305

SN - 0013-5194

VL - 33

SP - 30

EP - 31

JO - Electronics Letters

JF - Electronics Letters

IS - 1

ER -

Parallel BIST architecture for CAMs

Abstract

All Science Journal Classification (ASJC) codes

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