Parallel Dynamic Logic (PDL) with speed-enhanced skewed static (SSS) logic

Chulwoo Kim, Seong Ook Jung, Kwang Hyun Baek, Sung Mo Kang

Research output: Contribution to journalConference article

2 Citations (Scopus)

Abstract

In this paper, we describe Parallel Dynamic Logic (PDL) which exhibits high speed, no charge sharing problem. PDL uses only parallel-connected transistors for logic evaluation and is a good candidate for high-speed low-voltage operation. It has less back-bias effect compared to other logic styles which use stacked transistors. Furthermore, PDL needs no signal ordering nor tapering. PDL with speed-enhanced skewed static logic renders straightforward logic synthesis without area penalty due to logic duplication. Our experimental results on two 32-bit carry look ahead adders using 0.25 μm CMOS technology showed that PDL with speed-enhanced skewed static (SSS) logic improves performance over clock-delayed (CD)-domino by 15-27% and power×delay by 20-37%.

Original languageEnglish
Pages (from-to)I-756-I-759
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume1
Publication statusPublished - 2000 Jan 1
EventProceedings of the IEEE 2000 Internaitonal Symposium on Circuits and Systems - Geneva, Switz
Duration: 2000 May 282000 May 31

    Fingerprint

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this