Parallel in-order execution architecture for low-power processor

Kyungmin Lee, Ipoom Jeong, Won Woo Ro

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Mobile devices, such as smartphones and tablet PCs, have been widely used in everyday life. These devices are required to provide high performance for better user experience. Thereby, Application Processors (APs) equipped in mobile devices consist of a number of out-of-order superscalar cores that execute programs in a high performance. On the other hand, out-of-order cores consume much more power than in-order cores, due to their capability for dynamic scheduling of instructions. Dynamic instruction scheduling requires complex and expensive logics, such as instruction queue and wakeup/select logic. These structures consume more than 40% of total power dissipation of the out-of-order core. To address this problem, we propose Parallel In-Order Execution Architecture by introducing Parallel In-order eXecution Units (PIXU). In our design, ready-to-execute instructions are immediately issued to PIXU without dynamic scheduling but by referring simple table, namely Register Status Table (RST). Our design significantly depletes the wakeup and selection operation counts, which results in the improvement of overall energy efficiency. Consequently, our evaluation shows that our design increases the performance by 13% while reducing energy consumption to 90% with slight area overhead of 3.8% (PIXU: 2.0%, RST: 1.8%) of total area.

Original languageEnglish
Title of host publicationProceedings - International SoC Design Conference 2017, ISOCC 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages65-66
Number of pages2
ISBN (Electronic)9781538622858
DOIs
Publication statusPublished - 2018 May 29
Event14th International SoC Design Conference, ISOCC 2017 - Seoul, Korea, Republic of
Duration: 2017 Nov 52017 Nov 8

Publication series

NameProceedings - International SoC Design Conference 2017, ISOCC 2017

Other

Other14th International SoC Design Conference, ISOCC 2017
CountryKorea, Republic of
CitySeoul
Period17/11/517/11/8

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

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  • Cite this

    Lee, K., Jeong, I., & Ro, W. W. (2018). Parallel in-order execution architecture for low-power processor. In Proceedings - International SoC Design Conference 2017, ISOCC 2017 (pp. 65-66). (Proceedings - International SoC Design Conference 2017, ISOCC 2017). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC.2017.8368829