Parallel test algorithm for pattern sensitive faults in semiconductor random access memories

Jong Cheol Lee, Yong Seok Kang, Sungho Kang

Research output: Contribution to journalConference article

5 Citations (Scopus)

Abstract

This paper suggests a new test algorithm for parallel testing of neighborhood pattern sensitive faults(NPSFs) in large size random access memories(RAMs). The algorithm tests an √n × √n bit oriented memory in O(√n) time to detect Type-2 static, passive and active NPSFs. The algorithm uses a Hamiltonian sequence for static and passive NPSFs and an Eulerian sequence for active NPSFs. A group of cells are accessed simultaneously in a write operation. The cells sharing the same word line are read in parallel and mutually compared. The existing RAM architecture has been modified very little to achieve the parallel access and the mutual comparison.

Original languageEnglish
Pages (from-to)2721-2724
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume4
Publication statusPublished - 1997
EventProceedings of the 1997 IEEE International Symposium on Circuits and Systems, ISCAS'97. Part 4 (of 4) - Hong Kong, Hong Kong
Duration: 1997 Jun 91997 Jun 12

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'Parallel test algorithm for pattern sensitive faults in semiconductor random access memories'. Together they form a unique fingerprint.

  • Cite this