Parallel test algorithm for pattern sensitive faults in semiconductor random access memories

This paper suggests a new test algorithm for parallel testing of neighborhood pattern sensitive faults(NPSFs) in large size random access memories(RAMs). The algorithm tests an √n × √n bit oriented memory in O(√n) time to detect Type-2 static, passive and active NPSFs. The algorithm uses a Hamiltonian sequence for static and passive NPSFs and an Eulerian sequence for active NPSFs. A group of cells are accessed simultaneously in a write operation. The cells sharing the same word line are read in parallel and mutually compared. The existing RAM architecture has been modified very little to achieve the parallel access and the mutual comparison.