Path delay fault diagnosis using path scoring

Lim Yoseop; Lee Joohwan; Kang Sungho

doi:10.1109/SOCDC.2008.4815718

Path delay fault diagnosis using path scoring

Lim Yoseop, Lee Joohwan, Kang Sungho

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

With the increasing complexity of VLSI devices, more faults have appeared. The process of locating inputoutput in the chip that caused the delay fault is termed as fault diagnosis. In this paper, we propose a path delay fault algorithm using path scoring. The proposed diagnosis utilizes reasoning-based diagnosis technique and at fault diagnosis results to improve diagnosis the of delay-fault diagnosis. We propose a path scoring to increase first-hit-rate (FHR). Experimental results ISCAS85 and full-scan version of ISCAS89 benchmark prove the accuracy of the proposed algorithm.

Original language	English
Title of host publication	2008 International SoC Design Conference, ISOCC 2008
Pages	II199-II202
DOIs	https://doi.org/10.1109/SOCDC.2008.4815718
Publication status	Published - 2008
Event	2008 International SoC Design Conference, ISOCC 2008 - Busan, Korea, Republic of Duration: 2008 Nov 24 → 2008 Nov 25

Publication series

Name	2008 International SoC Design Conference, ISOCC 2008
Volume	2

Other

Other	2008 International SoC Design Conference, ISOCC 2008
Country	Korea, Republic of
City	Busan
Period	08/11/24 → 08/11/25

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Software

Access to Document

10.1109/SOCDC.2008.4815718

Fingerprint Dive into the research topics of 'Path delay fault diagnosis using path scoring'. Together they form a unique fingerprint.

Cite this

@inproceedings{cdfc87d5f4914f61872a294810c8499e,

title = "Path delay fault diagnosis using path scoring",

abstract = "With the increasing complexity of VLSI devices, more faults have appeared. The process of locating inputoutput in the chip that caused the delay fault is termed as fault diagnosis. In this paper, we propose a path delay fault algorithm using path scoring. The proposed diagnosis utilizes reasoning-based diagnosis technique and at fault diagnosis results to improve diagnosis the of delay-fault diagnosis. We propose a path scoring to increase first-hit-rate (FHR). Experimental results ISCAS85 and full-scan version of ISCAS89 benchmark prove the accuracy of the proposed algorithm.",

author = "Lim Yoseop and Lee Joohwan and Kang Sungho",

year = "2008",

doi = "10.1109/SOCDC.2008.4815718",

language = "English",

isbn = "9781424425990",

series = "2008 International SoC Design Conference, ISOCC 2008",

pages = "II199--II202",

booktitle = "2008 International SoC Design Conference, ISOCC 2008",

}

TY - GEN

T1 - Path delay fault diagnosis using path scoring

AU - Yoseop, Lim

AU - Joohwan, Lee

AU - Sungho, Kang

PY - 2008

Y1 - 2008

N2 - With the increasing complexity of VLSI devices, more faults have appeared. The process of locating inputoutput in the chip that caused the delay fault is termed as fault diagnosis. In this paper, we propose a path delay fault algorithm using path scoring. The proposed diagnosis utilizes reasoning-based diagnosis technique and at fault diagnosis results to improve diagnosis the of delay-fault diagnosis. We propose a path scoring to increase first-hit-rate (FHR). Experimental results ISCAS85 and full-scan version of ISCAS89 benchmark prove the accuracy of the proposed algorithm.

AB - With the increasing complexity of VLSI devices, more faults have appeared. The process of locating inputoutput in the chip that caused the delay fault is termed as fault diagnosis. In this paper, we propose a path delay fault algorithm using path scoring. The proposed diagnosis utilizes reasoning-based diagnosis technique and at fault diagnosis results to improve diagnosis the of delay-fault diagnosis. We propose a path scoring to increase first-hit-rate (FHR). Experimental results ISCAS85 and full-scan version of ISCAS89 benchmark prove the accuracy of the proposed algorithm.

UR - http://www.scopus.com/inward/record.url?scp=67650668047&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=67650668047&partnerID=8YFLogxK

U2 - 10.1109/SOCDC.2008.4815718

DO - 10.1109/SOCDC.2008.4815718

M3 - Conference contribution

AN - SCOPUS:67650668047

SN - 9781424425990

T3 - 2008 International SoC Design Conference, ISOCC 2008

SP - II199-II202

BT - 2008 International SoC Design Conference, ISOCC 2008

T2 - 2008 International SoC Design Conference, ISOCC 2008

Y2 - 24 November 2008 through 25 November 2008

ER -