Path-delay fault simulation for a standard scan design methodology

Sungho Kang, Wai On Law, Bill Underwood

Research output: Contribution to conferencePaper

2 Citations (Scopus)

Abstract

Inspite of using scan designs, there remain serious problems concerning the generation and confirmation of test vectors for potential timing problems. Most of the available test generators and the only fault simulators reported for path-delay faults in scan designs rely upon the use of augmented scan flip-flops to convert the timing vector problem to a purely combinational one. This paper describes a path-delay fault simulator for standard scan environments, based on the parallel-pattern-single-fault-propagation technique.

Original languageEnglish
Pages359-362
Number of pages4
Publication statusPublished - 1994 Dec 1
EventProceedings of the IEEE International Conference on Computer Design: VLSI in Computers and Processors - Cambridge, MA, USA
Duration: 1994 Oct 101994 Oct 12

Other

OtherProceedings of the IEEE International Conference on Computer Design: VLSI in Computers and Processors
CityCambridge, MA, USA
Period94/10/1094/10/12

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'Path-delay fault simulation for a standard scan design methodology'. Together they form a unique fingerprint.

  • Cite this

    Kang, S., Law, W. O., & Underwood, B. (1994). Path-delay fault simulation for a standard scan design methodology. 359-362. Paper presented at Proceedings of the IEEE International Conference on Computer Design: VLSI in Computers and Processors, Cambridge, MA, USA, .